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    NETWORK DEVICE INTERMEDIARY FOR MEMORY ACCESS REQUESTS
    11.
    发明申请
    NETWORK DEVICE INTERMEDIARY FOR MEMORY ACCESS REQUESTS 有权

    公开(公告)号：US20210089236A1

    公开(公告)日：2021-03-25

    申请号：US17112235

    申请日：2020-12-04

    Applicant: Intel Corporation

    Inventor： Ziye YANG ,  Shaopeng HE ,  Changpeng LIU ,  Xiaodong LIU

    IPC: G06F3/06

    Abstract: Examples described herein relate to receiving memory access requests in a first number of connections from one or more front-end clients destined to a storage system and consolidating the memory access requests to a second number of connections between a network device and the storage system, wherein the second number is less than the first number. In some examples, consolidating the memory access requests includes combining read commands with other read commands destined to the storage system among connections of the first number of connections and combining write commands with other write commands destined to a same storage system among connections of the first number of connections. In some examples, consolidating the memory access requests includes performing protocol conversion to a format accepted by the storage system. In some examples, read or write commands are identified based on content of a header of a received packet, wherein the received packet includes a read or write command.

    COMPUTER PROGRAM PRODUCT, SYSTEM, AND METHOD TO MANAGE ACCESS TO STORAGE RESOURCES FROM MULTIPLE APPLICATIONS
    12.
    发明申请
    COMPUTER PROGRAM PRODUCT, SYSTEM, AND METHOD TO MANAGE ACCESS TO STORAGE RESOURCES FROM MULTIPLE APPLICATIONS 有权

    公开(公告)号：US20210072927A1

    公开(公告)日：2021-03-11

    申请号：US16643470

    申请日：2017-09-27

    Applicant: INTEL CORPORATION

    Inventor： Ziye YANG ,  Gang CAO ,  Cunyin CHANG ,  Changpeng LIU ,  James HARRIS

    IPC: G06F3/06 ,  G06F9/50

    Abstract: A computer program product, system, and method to manage access to storage resources from multiple applications. A plurality of virtual controllers is generated in a host memory space. Each virtual controller includes at least one virtual namespace that maps to a physical namespace in a physical controller. Applications are assigned to the virtual controllers. For each application of the applications assigned one of the virtual controllers, a virtual submission queue is generated to communicate with the virtual controller assigned to the application. An Input/Output (I/O) request to a target virtual namespace in one of the virtual submission queues is added to a physical submission queue for the physical controller having the physical namespace for which the target virtual namespace was generated.

    INTERMEDIARY FOR STORAGE COMMAND TRANSFERS
    13.
    发明申请
    INTERMEDIARY FOR STORAGE COMMAND TRANSFERS 审中-公开

    公开(公告)号：US20200319812A1

    公开(公告)日：2020-10-08

    申请号：US16909693

    申请日：2020-06-23

    Applicant: Intel Corporation

    Inventor： Shaopeng HE ,  Yadong LI ,  Ziye YANG ,  Changpeng LIU ,  Banghao YING ,  Robert O. SHARP

    IPC: G06F3/06

    Abstract: Examples described herein relate to accessing an initiator as a Non-Volatile Memory Express (NMVe) device. In some examples, the initiator is configured with an address space, configured in kernel or user space, for access by a virtualized execution environment. In some examples, the initiator to copy one or more storage access commands from the virtualized execution environment into a queue for access by a remote direct memory access (RDMA) compatible network interface. In some examples, the network interface to provide Non-Volatile Memory Express over Fabrics (NVMe-oF) compatible commands based on the one or more storage access commands to a target storage device. In some examples, the initiator is created as a mediated device in kernel space or user space of a host system. In some examples, configuration of a physical storage pool address of the target storage device for access by the virtualized execution environment occurs by receipt of the physical storage pool address in a configuration command. In some examples, configuration of the target storage device for access by the virtualized execution environment occurs by receipt of a storage pool internal NVMe Qualified Name in the configuration command.

    PACKET PROCESSING CONFIGURATIONS
    15.
    发明申请
    PACKET PROCESSING CONFIGURATIONS 有权

    公开(公告)号：US20230043461A1

    公开(公告)日：2023-02-09

    申请号：US17971438

    申请日：2022-10-21

    Applicant: Intel Corporation

    Inventor： Luyao ZHONG ,  Ruijing GUO ,  Yongli HE ,  Hejie XU ,  Ziye YANG

    IPC: H04L47/62 ,  H04L49/90

    Abstract: Examples described herein relate to an interface and a network interface device coupled to the interface and comprising circuitry. In some examples, the circuitry is to receive packet data to be egressed, wherein the packet data does not specify a destination for the packet data and process the packet data to be egressed to generate a mapping of ingress packet-to-target based on a determination.

    SHARING CONTAINER DATA INSIDE A TENANT'S POD UNDER DIFFERENT TRUSTED EXECUTION ENVIRONMENTS (TEES)
    16.
    发明申请
    SHARING CONTAINER DATA INSIDE A TENANT'S POD UNDER DIFFERENT TRUSTED EXECUTION ENVIRONMENTS (TEES) 有权

    公开(公告)号：US20220391494A1

    公开(公告)日：2022-12-08

    申请号：US17889989

    申请日：2022-08-17

    Applicant: Intel Corporation

    Inventor： Ziye YANG ,  Malini K. BHANDARU ,  Ned SMITH

    IPC: G06F21/53

    Abstract: In a multitenant environment, confidential containers for the tenant having a trusted execution environment (TEE) which have security attested, can share data within the pod or between pods. The ability to share data for confidential containers of the same tenant eliminates the need to have multiple copies for different confidential containers. Thus, a storage device can store shared data specific to a tenant of the multitenant environment, and a caching service backed by protected hardware can manage access to the shared data. Management of the shared data can include attesting a key for a confidential container to verify that the confidential container is part of the TEE for a pod for the tenant, and access the shared data from the storage device for the confidential container based on the attested key.

    DATA ACCESS TECHNOLOGIES
    18.
    发明申请
    DATA ACCESS TECHNOLOGIES 有权

    公开(公告)号：US20220210097A1

    公开(公告)日：2022-06-30

    申请号：US17477782

    申请日：2021-09-17

    Applicant: Intel Corporation

    Inventor： Ziye YANG

    IPC: H04L49/90 ,  H04L49/103 ,  H04L49/9005 ,  H04L9/40 ,  H04L67/1097

    Abstract: Examples described herein relate to at least one processor and circuitry, when operational, to: cause a first number of processors of the at least one processor to access queues exclusively allocated for packets to be processed by the first number of processors; cause a second number of processors of the at least one processor to identify commands consistent with Non-volatile Memory Express (NVMe) over Quick User Data Protocol Internet Connections (QUIC), wherein the commands are received in the packets and the second number is based at least in part on a rate of received commands; and cause performance of the commands using a third number of processors. In some examples, the circuitry, when operational, is to: based on detection of a new connection on a first port, associate the new connection with a second port, wherein the second port is different than the first port and select at least one processor to identify and process commands received on the new connection.

    ADAPTIVE PROCESSOR RESOURCE UTILIZATION
    19.
    发明申请
    ADAPTIVE PROCESSOR RESOURCE UTILIZATION 审中-公开

    公开(公告)号：US20200218676A1

    公开(公告)日：2020-07-09

    申请号：US16825538

    申请日：2020-03-20

    Applicant: Intel Corporation

    Inventor： Gang CAO ,  James R. HARRIS ,  Ziye YANG ,  Vishal VERMA ,  Changpeng LIU ,  Chong HAN ,  Benjamin WALKER

    IPC: G06F13/16 ,  G06F9/50

    Abstract: Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.

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