公开(公告)号：US08476141B2

公开(公告)日：2013-07-02

申请号：US13737785

申请日：2013-01-09

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L21/20 ,  H01L21/31

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US20130143384A1

公开(公告)日：2013-06-06

申请号：US13737785

申请日：2013-01-09

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US09224878B2

公开(公告)日：2015-12-29

申请号：US13727962

申请日：2012-12-27

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

IPC: H01L21/20 ,  H01L29/92 ,  H01L49/02 ,  H01L51/52 ,  H01L51/00

CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

公开(公告)号：US08836002B2

公开(公告)日：2014-09-16

申请号：US13738794

申请日：2013-01-10

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Karthik Ramani ,  Hanhong Chen ,  Wim Deweerd ,  Nobumichi Fuchigami ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/94 ,  H01G4/12 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01G4/1218 ,  H01G4/33 ,  H01L28/60 ,  H01L28/75 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

公开(公告)号：US20130140619A1

公开(公告)日：2013-06-06

申请号：US13738866

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。