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公开(公告)号：US20140187018A1
公开(公告)日：2014-07-03
申请号：US13731452
申请日：2012-12-31
发明人： Sandra G. Malhotra , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L49/02
摘要： A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.
摘要翻译： 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。
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公开(公告)号：US20130270673A1
公开(公告)日：2013-10-17
申请号：US13915050
申请日：2013-06-11
发明人： Xiangxin Rui , Hiroyuki Ode
IPC分类号： H01L49/02
摘要： A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode layers are conductive molybdenum oxide.
摘要翻译： 形成用于MIM DRAM电容器的金属氧化物第一电极层，其中第一和/或第二电极层含有一个或多个掺杂剂，直到总掺杂浓度，其将不会阻止电极层在随后的退火步骤期间结晶。 一种或多种掺杂剂具有大于约5.0eV的功函数。 一种或多种掺杂剂具有小于约1000μmOcm的电阻率。 有利地，电极层是导电性氧化钼。
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公开(公告)号：US08476141B2
公开(公告)日：2013-07-02
申请号：US13737785
申请日：2013-01-09
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
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公开(公告)号：US20130143384A1
公开(公告)日：2013-06-06
申请号：US13737785
申请日：2013-01-09
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L49/02
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
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公开(公告)号：US20130140619A1
公开(公告)日：2013-06-06
申请号：US13738866
申请日：2013-01-10
申请人： Intermolecular, Inc.
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC分类号： H01L49/02
摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
摘要翻译： 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。
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6.发明申请公开(公告)号：US20130095632A1
公开(公告)日：2013-04-18
申请号：US13708035
申请日：2012-12-07
申请人： Intermolecular, Inc.
发明人： Xiangxin Rui , Hanhong Chen , Pragati Kumar , Sandra G. Malhotra
IPC分类号： H01L21/02
CPC分类号： H01L21/02 , B82Y99/00 , C01G23/047 , C01P2002/72 , C23C16/0272 , C23C16/34 , C23C16/405 , C23C16/45525 , H01L21/02186 , H01L21/0228 , H01L27/1085 , H01L28/40
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.
摘要翻译： 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。
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7.发明申请公开(公告)号：US20130072015A1
公开(公告)日：2013-03-21
申请号：US13675852
申请日：2012-11-13
申请人： Intermolecular, Inc.
发明人： Hanhong Chen , Toshiyuki Hirota , Pragati Kumar , Xiangxin Rui , Sunil Shanker
IPC分类号： H01L21/285
CPC分类号： H01L28/60 , C23C16/405 , H01L27/10852 , H01L28/40
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.
摘要翻译： 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。
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公开(公告)号：US20130059066A1
公开(公告)日：2013-03-07
申请号：US13658595
申请日：2012-10-23
申请人： Intermolecular, Inc
发明人： Xiangxin Rui , Iain Buchanan , Moo-Sung Kim , Xinjian Lei , Laura Matz , Sunil Shanker
IPC分类号： B05D5/12
CPC分类号： C23C16/45531 , C23C16/409 , H01L21/02197 , H01L21/0228 , H01L21/02356 , H01L21/3142 , H01L21/31691 , H01L28/56
摘要： Embodiments of the current invention include methods of forming a strontium titanate (SrTiO3) film using atomic layer deposition (ALD). More particularly, the method includes forming a plurality of titanium oxide (TiO2) unit films using ALD and forming a plurality of strontium oxide (SrO) unit films using ALD. The combined thickness of the TiO2 and SrO unit films is less than approximately 5 angstroms. The TiO2 and SrO units films are then annealed to form a strontium titanate layer.
摘要翻译： 本发明的实施方案包括使用原子层沉积（ALD）形成钛酸锶（SrTiO 3）膜的方法。 更具体地说，该方法包括使用ALD形成多个氧化钛（TiO 2）单元膜并使用ALD形成多个氧化锶（SrO）单元膜。 TiO 2和SrO单元膜的组合厚度小于约5埃。 然后将TiO 2和SrO单元膜退火以形成钛酸锶层。
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公开(公告)号：US20130056852A1
公开(公告)日：2013-03-07
申请号：US13668488
申请日：2012-11-05
申请人： Intermolecular, Inc.
IPC分类号： H01L29/92
CPC分类号： H01L21/3141 , C23C16/02 , C23C16/405 , H01L21/02186 , H01L21/02271 , H01L21/02315 , H01L21/31604 , H01L28/91
摘要： Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.
摘要翻译： 描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角 并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种在暴露的金属上沉积氧化钛层，其中所述氧化钛层包含至少一部分金红石型氧化钛。
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公开(公告)号：US09012298B2
公开(公告)日：2015-04-21
申请号：US13731452
申请日：2012-12-31
发明人： Sandra G. Malhotra , Hiroyuki Ode , Xiangxin Rui
摘要： A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.
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