公开(公告)号：US20150254553A1

公开(公告)日：2015-09-10

申请号：US14202590

申请日：2014-03-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI

IPC: G06N3/08 ,  G06N3/063

CPC classification number: G06N3/08 ,  G06N3/0445 ,  G06N3/049 ,  G06N3/063 ,  G06N5/02

Abstract: A circuit is provided for that includes one or more TCAM arrays including one or more matchlines configured to model a neural network. Each of the one or more TCAM arrays models a connected group of neurons such that input search data into the one or more matchlines is modeled as neuron dendrite information, and the output from the one or more matchlines is modeled as neuron axon information. The circuit further includes one or more additional bits included within each of the one or more matchlines that are configured to model connectivity strength between each neuron dendrite and axon. The circuit also includes a real-time learning block included within each of the one or more TCAM arrays configured to modify the connectivity strength between each neuron dendrite and axon using wild-cards written and stored in the one or more additional bits.

Abstract translation: 提供了一种电路，其包括一个或多个TCAM阵列，其包括被配置为对神经网络建模的一个或多个匹配线。 一个或多个TCAM阵列中的每一个模拟连接的神经元组，使得到一个或多个匹配线的输入搜索数据被建模为神经元树突信息，并且来自一个或多个匹配线的输出被建模为神经轴突信息。 该电路还包括一个或多个附加位，其包括在一个或多个匹配线中的每一个中，其被配置为模拟每个神经元树突与轴突之间的连接强度。 该电路还包括一个或多个TCAM阵列中的每一个中包括的实时学习块，其被配置为使用写入并存储在一个或多个附加位中的通配符来修改每个神经元枝晶与轴突之间的连接强度。

公开(公告)号：US20170040059A1

公开(公告)日：2017-02-09

申请号：US14818764

申请日：2015-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Suparna BHATTACHARYA ,  Arvind KUMAR

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

Abstract translation: 公开了三元内容可寻址存储器（TCAM）结构和使用方法。 存储器架构包括一个或多个三元内容可寻址存储器（TCAM）字段，以及控制逻辑，其应用逐行识别数据掩蔽，并且基于匹配和不匹配的比特对匹配的接近进行评分。

公开(公告)号：US20160365146A1

公开(公告)日：2016-12-15

申请号：US14734504

申请日：2015-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Michael T. FRAGANO ,  Thomas M. MAFFITT

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C11/413 ,  G11C15/00

Abstract: A ternary content addressable memory (TCAM) structure may activate individual groups of subarrays in the TCAM structure, during a non-search mode, at configurable intervals of time. The activating causes the TCAM structure to select locations and sequences in which subarrays of the TCAM structure are activated or deactivated. When activating, the TCAM structure is configured to perform a dummy search within the particular subarray. The activating reduces a change in current during transition between a search mode and the non-search mode.

Abstract translation: 三元内容可寻址存储器（TCAM）结构可以在非搜索模式期间以可配置的时间间隔激活TCAM结构中的各个子阵列。 激活导致TCAM结构选择TCAM结构的子阵列被激活或去激活的位置和序列。 当激活时，TCAM结构被配置为在特定子阵列内执行虚拟搜索。 该激活减少了在搜索模式和非搜索模式之间的转换期间的电流变化。

公开(公告)号：US20150332767A1

公开(公告)日：2015-11-19

申请号：US14280130

申请日：2014-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI

IPC: G11C15/04 ,  G11C11/417

CPC classification number: G11C15/04 ,  G11C5/02 ,  G11C11/417

Abstract: A content addressable memory (CAM) search engine is disclosed. The CAM search engine includes a data compare plane having a content addressable memory die including an array of comparison cells. The CAM search engine further includes a memory stack on the data compare plane. The memory stack has stacked memory dies including memory banks. The array of comparison cells includes parallel interconnects. The parallel interconnects electrically connect to outputs of the memory banks. The comparison cells are time-shared among the one or more memory banks

Abstract translation: 公开了内容可寻址存储器（CAM）搜索引擎。 CAM搜索引擎包括具有包含比较单元阵列的内容可寻址存储器管芯的数据比较平面。 CAM搜索引擎还包括数据比较平面上的存储器堆栈。 存储器堆栈具有堆叠的存储器管芯，包括存储器组。 比较单元的阵列包括并联互连。 并联互连电连接到存储体的输出端。 比较单元在一个或多个存储体之间是时间共享的

公开(公告)号：US20150228357A1

公开(公告)日：2015-08-13

申请号：US14178955

申请日：2014-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Nathaniel R. CHADWICK ,  John B. DEFORGE ,  Ezra D.B. HALL ,  Kirk D. PETERSON

IPC: G11C29/04 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C29/06

Abstract: Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location. The method also includes determining that the location is unbalanced based on the characterizing. Further, the method includes inverting a logic state of the location. Additionally, the method includes changing a value of an inversion indicator corresponding to the location.

Abstract translation: 应力平衡场效应晶体管的方法，系统和结构受到偏置温度不稳定性引起的阈值电压偏移。 一种方法包括通过偏移位置的位线电压来表征存储器阵列中的位置的疲劳。 该方法还包括基于特征确定位置不平衡。 此外，该方法包括反转位置的逻辑状态。 此外，该方法包括改变对应于该位置的反转指示符的值。

公开(公告)号：US20130307580A1

公开(公告)日：2013-11-21

申请号：US13948567

申请日：2013-07-23

Applicant: International Business Machines Corporation

Inventor： Igor ARSOVSKI ,  Robert M. HOULE

IPC: H03K19/003

CPC classification number: H03K19/003 ,  G11C11/419

Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.