公开(公告)号：US20190267086A1

公开(公告)日：2019-08-29

申请号：US16411807

申请日：2019-05-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chung H. LAM ,  Scott C. LEWIS ,  Thomas M. MAFFITT ,  Jack MORRISH

IPC: G11C13/00 ,  G11C11/56

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

公开(公告)号：US20160365146A1

公开(公告)日：2016-12-15

申请号：US14734504

申请日：2015-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor ARSOVSKI ,  Michael T. FRAGANO ,  Thomas M. MAFFITT

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C11/413 ,  G11C15/00

Abstract: A ternary content addressable memory (TCAM) structure may activate individual groups of subarrays in the TCAM structure, during a non-search mode, at configurable intervals of time. The activating causes the TCAM structure to select locations and sequences in which subarrays of the TCAM structure are activated or deactivated. When activating, the TCAM structure is configured to perform a dummy search within the particular subarray. The activating reduces a change in current during transition between a search mode and the non-search mode.

Abstract translation: 三元内容可寻址存储器（TCAM）结构可以在非搜索模式期间以可配置的时间间隔激活TCAM结构中的各个子阵列。 激活导致TCAM结构选择TCAM结构的子阵列被激活或去激活的位置和序列。 当激活时，TCAM结构被配置为在特定子阵列内执行虚拟搜索。 该激活减少了在搜索模式和非搜索模式之间的转换期间的电流变化。

公开(公告)号：US20190355416A1

公开(公告)日：2019-11-21

申请号：US16526273

申请日：2019-07-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chung H. LAM ,  Scott C. LEWIS ,  Thomas M. MAFFITT ,  Jack MORRISH

IPC: G11C13/00 ,  G11C11/56

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

公开(公告)号：US20180068725A1

公开(公告)日：2018-03-08

申请号：US15812213

申请日：2017-11-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chung H. LAM ,  Scott C. LEWIS ,  Thomas M. MAFFITT ,  Jack MORRISH

IPC: G11C13/00 ,  G11C11/56

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

公开(公告)号：US20190355417A1

公开(公告)日：2019-11-21

申请号：US16526303

申请日：2019-07-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chung H. LAM ,  Scott C. LEWIS ,  Thomas M. MAFFITT ,  Jack MORRISH

IPC: G11C13/00 ,  G11C11/56

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

公开(公告)号：US20190267087A1

公开(公告)日：2019-08-29

申请号：US16411844

申请日：2019-05-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chung H. LAM ,  Scott C. LEWIS ,  Thomas M. MAFFITT ,  Jack MORRISH

IPC: G11C13/00 ,  G11C11/56

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

公开(公告)号：US20150206582A1

公开(公告)日：2015-07-23

申请号：US14157605

申请日：2014-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chung H. LAM ,  Scott C. LEWIS ,  Thomas M. MAFFITT ,  Jack R. MORRISH

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.

Abstract translation: 这里公开了用于多位相变存储器的结构和方法。 一种方法包括建立在写入周期上递增地斜坡的写参考电压。 写参考电压的增量对应于多位相变存储器的存储单元的离散电阻状态。