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公开(公告)号：US09256397B2
公开(公告)日：2016-02-09
申请号：US14095474
申请日：2013-12-03
CPC分类号： G06F7/483 , G06F7/509 , G06F7/5324 , G06F7/5332 , G06F7/5443
摘要： A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
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公开(公告)号：US10649738B2
公开(公告)日：2020-05-12
申请号：US16380267
申请日：2019-04-10
摘要： A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.
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公开(公告)号：US10303438B2
公开(公告)日：2019-05-28
申请号：US15406910
申请日：2017-01-16
摘要： A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.
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公开(公告)号：US09952829B2
公开(公告)日：2018-04-24
申请号：US15011735
申请日：2016-02-01
CPC分类号： G06F7/4876 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/485 , G06F7/5443 , G06F2207/483
摘要： A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.
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公开(公告)号：US20150363170A1
公开(公告)日：2015-12-17
申请号：US14735271
申请日：2015-06-10
IPC分类号： G06F7/535
CPC分类号： G06F7/5375 , G06F7/48 , G06F7/533
摘要： Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.
摘要翻译： 在数据处理单元中执行算术运算，包括以每次迭代给定的位数来计算用于执行算术运算的迭代次数。 每次迭代的位数是正的自然数。 对在数据处理单元中表示的比特序列中的数字的连续数位位置进行计数。 序列的长度是每次迭代的位数的倍数。 计算连续数字位数的数除以每次迭代的位数的商，以及除法的剩余部分。
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公开(公告)号：US10379811B2
公开(公告)日：2019-08-13
申请号：US15815120
申请日：2017-11-16
摘要： A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.
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公开(公告)号：US10303440B2
公开(公告)日：2019-05-28
申请号：US15409778
申请日：2017-01-19
摘要： A combined residue circuit configured to receive data and to provide a first residue result and a second residue result. The first residue result is based on a first modulo value, and the second residue result is based on a second modulo value. The first modulo value is different than the second modulo value. The first residue result is to be used to protect data based on a first radix, and the second residue result is to be used to protect data based on a second radix different from the first radix.
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公开(公告)号：US10235135B2
公开(公告)日：2019-03-19
申请号：US15651646
申请日：2017-07-17
摘要： A unit operates on a sum term and a carry term separated into a high part and a low part of a product and performs a method that includes iteratively computing a carry save product and separating the carry save product into the high part and the low part: an intermediate product. The unit generates an intermediate wide result by performing a wide addition of the intermediate product to generate an unrounded sum for the high part (i.e., a fused-multiply-add high part) and the low part (i.e., a fused-multiply-add high part). The unit pre-aligns the intermediate wide result on two fixed length shifters such that the fused-multiply-add high part and the fused-multiply-add low part are pre-aligned to each fit on one shifter of the two fixed length shifters.
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公开(公告)号：US10095475B2
公开(公告)日：2018-10-09
申请号：US15840033
申请日：2017-12-13
摘要： Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.
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公开(公告)号：US09959093B2
公开(公告)日：2018-05-01
申请号：US15197290
申请日：2016-06-29
CPC分类号： G06F7/4876 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/485 , G06F7/5443 , G06F2207/483
摘要： A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.
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