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公开(公告)号：US20240184971A1
公开(公告)日：2024-06-06
申请号：US18062098
申请日：2022-12-06
IPC分类号： G06F30/392
CPC分类号： G06F30/392
摘要： A method for bit line alignment during the design of an integrated circuit is provided. Aspects include receiving a chip design for the integrated circuit and receiving an intended orientation of the integrated circuit. Aspects also include identifying one or more elements of the chip design that include word lines that are oriented in a substantially gravitational direction and modifying the chip design to perform one or more of rotating the one or more elements such that the word lines are no longer oriented in a substantially gravitational direction and rotating the one or more elements such that the word lines are oriented in a direction substantially perpendicular to the gravitational direction. Aspects further include causing the fabrication of the integrated circuit based on the modified chip design.
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公开(公告)号：US11379123B2
公开(公告)日：2022-07-05
申请号：US17193666
申请日：2021-03-05
发明人： Steven R. Carlough , Susan M. Eickhoff , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
摘要： One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.
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公开(公告)号：US11269561B2
公开(公告)日：2022-03-08
申请号：US17129248
申请日：2020-12-21
摘要： A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.
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公开(公告)号：US10698440B2
公开(公告)日：2020-06-30
申请号：US15866838
申请日：2018-01-10
发明人： Steven R. Carlough , Susan M. Eickhoff , Michael B. Spear , Gary A. Van Huben , Stephen D. Wyatt
摘要： A calibration controller determines a latest arriving data strobe at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary. The calibration controller aligns the chip clock with a high speed clock for controlling an unload pointer to unload the data from the second data buffer to a serializer in the read data path, wherein the data cross a second clock boundary from the second data buffer to the serializer, to minimize a latency in the read data path across a second clock boundary.
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公开(公告)号：US10541782B2
公开(公告)日：2020-01-21
申请号：US15817416
申请日：2017-11-20
摘要： Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.
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公开(公告)号：US10419035B2
公开(公告)日：2019-09-17
申请号：US15817399
申请日：2017-11-20
摘要： Aspects of the invention include calculating, by a transmitter, source cyclic redundancy code (CRC) bits for payload bits. The source CRC bits include source CRC bits for a first type of CRC check and source CRC bits for a second type of CRC check. The source CRC bits are stored at the transmitter. The payload bits and the source CRC bits for the first type of CRC check are transmitted to the receiver. The receiver performs the first type of CRC check based at least in part on the payload bits and the source CRC bits for the first type of CRC check. The receiver also calculates and stores at the receiver calculated CRC bits for the second type of CRC check. If the first type of CRC check indicates an error, a comparison of the source and calculated CRC bits for the second type of CRC check is initiated.
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7.发明授权公开(公告)号：US10395698B2
公开(公告)日：2019-08-27
申请号：US15825894
申请日：2017-11-29
发明人： Steven R. Carlough , Susan M. Eickhoff , Warren E. Maule , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
摘要： One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
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公开(公告)号：US10387154B2
公开(公告)日：2019-08-20
申请号：US15069581
申请日：2016-03-14
发明人： James W. Bishop , Marcy E. Byers , Steven R. Carlough , Paul M. Kennedy , Albert J. Van Norstrand, Jr. , Phillip G. Williams
摘要： Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.
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9.发明授权公开(公告)号：US10365892B2
公开(公告)日：2019-07-30
申请号：US15406818
申请日：2017-01-16
摘要： Processing within a computing environment is facilitated. An operand of an instruction is obtained, which includes decimal floating point data encoded in a compressed format. An operation is performed on the operand absent decompressing a source value of a trailing significand of the decimal floating point data in the compressed format.
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公开(公告)号：US20190212769A1
公开(公告)日：2019-07-11
申请号：US15866838
申请日：2018-01-10
发明人： Steven R. Carlough , Susan M. Eickhoff , Michael B. Spear , Gary A. Van Huben , Stephen D. Wyatt
摘要： A calibration controller determines a latest arriving data strobe at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe, wherein data crosses a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary. The calibration controller aligns the chip clock with a high speed clock for controlling an unload pointer to unload data from the second data buffer to a serializer in the read data path, wherein data crosses a second clock boundary from the second data buffer to the serializer, to minimize a latency in the read data path across a second clock boundary.
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