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    Single flux quantum circuitry for quantized flux bias control
    13.
    发明授权
    Single flux quantum circuitry for quantized flux bias control 有权

    公开(公告)号：US12150389B2

    公开(公告)日：2024-11-19

    申请号：US18128447

    申请日：2023-03-30

    Applicant: International Business Machines Corporation

    Inventor： Matthew Beck ,  Raphael Peter Robertazzi ,  John Francis Bulzacchelli

    IPC: H10N60/12 ,  G06N10/40 ,  H03K3/38 ,  H03K19/195 ,  H10N60/80

    Abstract: A system comprises a superconducting quantizing inductor and superconducting control circuitry, which is coupled to the superconducting quantizing inductor to form a superconducting loop, and which is configured to selectively inject a quantized amount of positive or negative current into the superconducting loop to generate a quantized circulating current in the superconducting loop. The quantized circulating current comprises a time-varying or static circulating current. The superconducting control circuitry comprises first and second current generator circuits which comprise a first and second plurality of Josephson junctions, respectively, which are configured to inject quantized amounts of positive current and negative current into the superconducting loop in response to single flux quantum pulses. The first and second current generator circuits comprise respective first and second current distribution networks that are configured to distribute circulating current in the superconducting loop to the respective Josephson junctions without causing switching of the Josephson junctions.

    METASTABILITY-FREE CLOCKLESS SINGLE FLUX QUANTUM LOGIC CIRCUITRY
    15.
    发明公开
    METASTABILITY-FREE CLOCKLESS SINGLE FLUX QUANTUM LOGIC CIRCUITRY 审中-公开

    公开(公告)号：US20240235558A9

    公开(公告)日：2024-07-11

    申请号：US17971700

    申请日：2022-10-24

    Applicant: International Business Machines Corporation

    Inventor： Sergey Rylov ,  John Francis Bulzacchelli ,  Matthew Beck

    IPC: H03K19/195 ,  H03K19/20

    CPC classification number: H03K19/195 ,  H03K19/20

    Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

    Josphson band pass to band stop filter
    17.
    发明授权
    Josphson band pass to band stop filter 有权

    公开(公告)号：US11831291B2

    公开(公告)日：2023-11-28

    申请号：US17543095

    申请日：2021-12-06

    Applicant: International Business Machines Corporation

    Inventor： Matthew Beck

    IPC: H03K17/92 ,  H03H11/04

    CPC classification number: H03H11/04 ,  H03K17/92 ,  H03H2011/0488

    Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can facilitate selective switching between band pass and band stop filter modes and/or can provide reflectionless or near reflectionless function. A device can comprise a filter circuit coupled between a pair of ports and comprising a direct current superconducting quantum interference device (DC SQUID), wherein the filter circuit is selectively activatable by varying the inductance of the DC SQUID. Applying flux bias to the DC SQUID can allow for the switching between the band pass and band stop filter modes.

    QUANTUM CIRCUIT WITH JOSEPHSON MULTIPOLE ISOLATOR
    18.
    发明申请
    QUANTUM CIRCUIT WITH JOSEPHSON MULTIPOLE ISOLATOR 有权

    公开(公告)号：US20230119964A1

    公开(公告)日：2023-04-20

    申请号：US17505358

    申请日：2021-10-19

    Applicant: International Business Machines Corporation

    Inventor： Matthew Beck ,  Michael Karunendra Selvanayagam

    IPC: H01L39/22 ,  G01R33/035 ,  G06N10/00

    Abstract: One or more systems, devices, methods of use and/or methods of fabrication provided herein relate to a device that can facilitate qubit measurement with isolation imposed between a quantum processor and a respective qubit measurement circuit and/or which respective qubit measurement circuit can have a small footprint, such as within a respective cryogenic chamber of a quantum system. According to one embodiment, a device comprises an isolator circuit having a bandpass filter configuration coupled between a pair of ports and the bandpass filter configuration comprising two or more poles. Two or more shunt resonators can be realized as the two or more poles, wherein the two or more shunt resonators can comprise DC SQUIDs and can be coupled together with one or more admittance inverters. A non-reciprocal signal transmission can be generated between the two ports by RF pumping the DC SQUIDs.

    Metastability-free clockless single flux quantum logic circuitry
    19.
    发明授权
    Metastability-free clockless single flux quantum logic circuitry 有权

    公开(公告)号：US12231123B2

    公开(公告)日：2025-02-18

    申请号：US17971700

    申请日：2022-10-24

    Applicant: International Business Machines Corporation

    Inventor： Sergey Rylov ,  John Francis Bulzacchelli ,  Matthew Beck

    IPC: H03K19/195 ,  G06F1/10 ,  G06N10/20 ,  G06N10/40 ,  H03K19/20

    Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

    METASTABILITY-FREE CLOCKLESS SINGLE FLUX QUANTUM LOGIC CIRCUITRY
    20.
    发明公开
    METASTABILITY-FREE CLOCKLESS SINGLE FLUX QUANTUM LOGIC CIRCUITRY 审中-公开

    公开(公告)号：US20240137027A1

    公开(公告)日：2024-04-25

    申请号：US17971700

    申请日：2022-10-23

    Applicant: International Business Machines Corporation

    Inventor： Sergey Rylov ,  John Francis Bulzacchelli ,  Matthew Beck

    IPC: H03K19/195 ,  H03K19/20

    CPC classification number: H03K19/195 ,  H03K19/20

    Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

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