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公开(公告)号：US10739397B2
公开(公告)日：2020-08-11
申请号：US15591226
申请日：2017-05-10
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James H. Stathis
Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
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公开(公告)号：US20200243383A1
公开(公告)日：2020-07-30
申请号：US16262560
申请日：2019-01-30
Applicant: International Business Machines Corporation
Inventor： Huai Huang , Takeshi Nogami , Alfred Grill , Benjamin D. Briggs , Nicholas A. Lanzillo , Christian Lavoie , Devika Sil , Prasad Bhosale , James Kelly
IPC: H01L21/768 , H01L23/522 , H01L23/532
Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.
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公开(公告)号：US20190122911A1
公开(公告)日：2019-04-25
申请号：US15791451
申请日：2017-10-24
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James Stathis
Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
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公开(公告)号：US20180328977A1
公开(公告)日：2018-11-15
申请号：US15591226
申请日：2017-05-10
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James H. Stathis
Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
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公开(公告)号：US20180211920A1
公开(公告)日：2018-07-26
申请号：US15412768
申请日：2017-01-23
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Takeshi Nogami , Christopher J. Penny , Michael Rizzolo
IPC: H01L23/532 , H01L23/522 , H01L21/768
CPC classification number: H01L23/53238 , H01L21/76847
Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
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Patent Agency Ranking
公开(公告)号：US11869783B2
公开(公告)日：2024-01-09
申请号：US17244084
申请日：2021-04-29
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James Stathis
CPC classification number: H01L21/67271 , G06N5/04 , G06N20/00
Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
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公开(公告)号：US10978393B2
公开(公告)日：2021-04-13
申请号：US16131553
申请日：2018-09-14
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Takeshi Nogami , Christopher J. Penny , Michael Rizzolo
IPC: H01L21/768 , H01L23/532 , H01L23/522
Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
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公开(公告)号：US10741751B2
公开(公告)日：2020-08-11
申请号：US16596152
申请日：2019-10-08
Applicant: International Business Machines Corporation
Inventor： Nicholas A. Lanzillo , Benjamin D. Briggs , Chih-Chao Yang , Hsueh-Chung Chen , Lawrence A. Clevenger
Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.
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19.发明授权公开(公告)号：US10720567B2
公开(公告)日：2020-07-21
申请号：US15972423
申请日：2018-05-07
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert
Abstract: Techniques for preventing switching of spins in a magnetic tunnel junction by stray magnetic fields using a thin film magnetic shield are provided. In one aspect, a method of forming a magnetic tunnel junction includes: forming a stack on a substrate, having a first magnetic layer, a tunnel barrier, and a second magnetic layer; etching the stack to partially pattern the magnetic tunnel junction in the stack, wherein the etching includes patterning the magnetic tunnel junction through the second magnetic layer, the tunnel barrier, and partway through the first magnetic layer; depositing a first spacer and a magnetic shield film onto the partially patterned magnetic tunnel junction; etching back the magnetic shield film and first spacer; complete etching of the magnetic tunnel junction through the first magnetic layer to form a fully patterned magnetic tunnel junction; and depositing a second spacer onto the fully patterned magnetic tunnel junction.
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公开(公告)号：US20200091079A1
公开(公告)日：2020-03-19
申请号：US16690925
申请日：2019-11-21
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Takeshi Nogami , Christopher J. Penny , Michael Rizzolo
IPC: H01L23/532 , H01L21/768 , H01L23/522
Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
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