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1.发明公开公开(公告)号：US20240147876A1
公开(公告)日：2024-05-02
申请号：US17978560
申请日：2022-11-01
发明人： Kangguo Cheng , Michael Rizzolo
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/1226 , H01L45/1675
摘要： A memory cell structure includes a substrate having formed thereon a first electrode and second electrodes physically spaced apart. A phase change material (PCM) cell is formed on the substrate and forms a bridge extending between the first and second electrodes, the phase change material including a first end electrically contacting the first electrode and a second end contacting the second electrode. The phase change material cell includes a thinned surface portion where a surface topography of the phase change material cell is decreased relative to a surface topography of the phase change material cell surface at the first and second ends. The PCM thickness is intentionally gradually tapered to localize the formation of the phase change region. During PCM programming, corresponding to the weight update in machine learning, the phase change of the PCM occurs at the thinnest surface portion and gradually propagates towards the electrodes.
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公开(公告)号：US11502242B2
公开(公告)日：2022-11-15
申请号：US16828489
申请日：2020-03-24
摘要： A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.
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公开(公告)号：US20220238794A1
公开(公告)日：2022-07-28
申请号：US17248479
申请日：2021-01-27
摘要： An embodiment of the invention may include a magnetic random-access memory (MRAM) structure and method of making the structure. The MRAM structure may include a magnetic tunnel junction stack. The MRAM structure may include a magnetic liner located between the magnetic tunnel junction stack and a top contact, where the magnetic liner may be a ferromagnetic material. This may enable the magnetic liner to act as an independent variable to balance many of the magnetic parameters in the MTJ film stack in order to achieve zero magnetic field at the MTJ layer.
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公开(公告)号：US20220109099A1
公开(公告)日：2022-04-07
申请号：US17552027
申请日：2021-12-15
摘要： A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.
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公开(公告)号：US20210399212A1
公开(公告)日：2021-12-23
申请号：US16903516
申请日：2020-06-17
摘要： A method of manufacturing a magnetic random access memory device includes depositing a liner on an intermediate device including an opening in a sacrificial dielectric layer, depositing a conductive metal over the liner and in the opening, removing a portion of the conductive metal while preserving the liner and a thickness of the sacrificial dielectric layer, removing a first portion of the liner by etching, wherein the liner is recessed into the opening, depositing a plurality of metallic tunnel junction layers, forming a hardmask on the plurality of metallic tunnel junction layers, and patterning the metallic tunnel junction layers to form a metallic tunnel junction stack and simultaneously clear a second portion of the liner and a portion the sacrificial dielectric layer.
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公开(公告)号：US20210370705A1
公开(公告)日：2021-12-02
申请号：US16888126
申请日：2020-05-29
IPC分类号： B42D25/369 , G06K19/18 , G06K19/12 , G06F21/12 , G06F21/44 , B42D25/333 , B42D25/373
摘要： An article is authenticated by providing a magnetic security mark in the form of an optically-passive randomly-generated nanoscale magnetic pattern. The pattern is pre-imaged and this reference image is uploaded to a secure database along with an identifier for the article such as a serial number. A user of the article verifies its authenticity by scanning it magnetically to obtain a scanned image of the magnetic pattern. The serial number is used to retrieve the previously uploaded reference image which is compared to the scanned image. If the images match, the article's authenticity is confirmed. A single article may have multiple magnetic security marks, each unique, placed at predetermined, non-uniform locations. The magnetic patterns are generated using thin film deposition of yttrium iron garnet. In one embodiment the article is a physical key having additional security features, such as mechanical features and a radio-frequency identification chip.
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公开(公告)号：US11121174B2
公开(公告)日：2021-09-14
申请号：US16690675
申请日：2019-11-21
发明人： Alexander Reznicek , Michael Rizzolo , Ruilong Xie
摘要： A memory cell is provided in which a bottom electrode of a magnetoresistive random access memory (MRAM) device is connected to one of the source/drain contact structures of a transistor, and a lower contact structure is connected to another of the source/drain contact structures of the transistor. In the present application, the MRAM device and the lower contact structure are present in the middle-of-the-line ((MOL) not the back-end-of-the-line (BEOL). Moreover, the bottom electrode of the MRAM device, and a lower portion of the lower contact structure are present in a same dielectric material (i.e., a MOL dielectric material).
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公开(公告)号：US20210265277A1
公开(公告)日：2021-08-26
申请号：US16799048
申请日：2020-02-24
IPC分类号： H01L23/532 , H01L23/538 , H01L21/768
摘要： A semiconductor structure includes an interlayer dielectric layer, a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer, and a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer. Each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio. Each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio. The second width is greater than the first width, and the second height is different than the first height.
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公开(公告)号：US20210249288A1
公开(公告)日：2021-08-12
申请号：US17244084
申请日：2021-04-29
发明人： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James Stathis
摘要： One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
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公开(公告)号：US11074387B2
公开(公告)日：2021-07-27
申请号：US16684919
申请日：2019-11-15
发明人： Prasad Bhosale , Michael Rizzolo , Chih-Chao Yang
IPC分类号： G06F30/367 , G06F30/398 , G06F119/18 , H01L21/66 , G06N5/02 , G06N20/00
摘要： A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
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