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165 条记录 (耗时 0.04 秒)

    WEAR RESISTANT, HEAT RESISTANT CONVEYOR CHAIN
    12.
    发明申请
    WEAR RESISTANT, HEAT RESISTANT CONVEYOR CHAIN 失效
    耐磨，耐热输送链

    公开(公告)号：US20090294258A1

    公开(公告)日：2009-12-03

    申请号：US12540461

    申请日：2009-08-13

    申请人： Takashi Nakagawa ,  Hiroki Ishida ,  Makoto Fujiwara ,  Ryutaro Nakamura ,  Nobuo Kitao ,  Tatsuo Nagata ,  Satoshi Nakatou

    发明人： Takashi Nakagawa ,  Hiroki Ishida ,  Makoto Fujiwara ,  Ryutaro Nakamura ,  Nobuo Kitao ,  Tatsuo Nagata ,  Satoshi Nakatou

    IPC分类号： B65G17/38

    CPC分类号： B65G17/38 ,  B65G2207/12 ,  B65G2207/48

    摘要： A wear resistant, heat resistant conveyor chain comprising a series of links, each having a heat resistant roller rotatably fitted onto a bush between inner plates. The links are interconnected in the longitudinal direction of the chain by outer plates, and connecting pins rotatably inserted into the bush. A wear resistant, heat resistant sleeve-shaped spacer protrudes beyond the end surfaces of the heat resistant rollers toward the right and left inner plates to eliminate any sliding contact between the end surface of the heat resistant roller and the inner side surface of the inner plate.

    摘要翻译： 一种耐磨，耐热的输送链，其包括一系列连接件，每个连接件具有可旋转地安装在内板之间的衬套上的耐热辊。 连杆通过外板在链条的纵向互连，并且连接销可旋转地插入衬套中。 耐磨，耐热的套筒型间隔件突出超过耐热辊的端面朝向左右内板，以消除耐热辊的端面与内板的内侧表面之间的任何滑动接触 。

    LSI design method and verification method
    16.
    发明授权
    LSI design method and verification method 有权
    LSI设计方法和验证方法

    公开(公告)号：US07281136B2

    公开(公告)日：2007-10-09

    申请号：US09779440

    申请日：2001-02-09

    申请人： Kentaro Shiomi ,  Akira Motohara ,  Makoto Fujiwara ,  Toshiyuki Yokoyama ,  Katsuya Fujimura

    发明人： Kentaro Shiomi ,  Akira Motohara ,  Makoto Fujiwara ,  Toshiyuki Yokoyama ,  Katsuya Fujimura

    IPC分类号： G06F12/14 ,  G06F17/50

    CPC分类号： G06F21/75 ,  G06F17/5022 ,  G06F21/6209

    摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.

    摘要翻译： 在LSI设计中采用加密处理，以便改进电路设计数据对传统示例的保密性。 在加密过程中，机密电路设计数据被加密以产生加密设计数据和加密密钥。 将加密的设计数据提供给进行设计/验证处理的用户。 钥匙也按要求提供。 在设计/验证过程中，对加密设计数据进行各种处理，而不会公开原始电路的内容。 在解码处理中，经受设计/验证处理的加密设计数据被解码以产生原始电路设计数据。

    Encryption circuit
    17.
    发明申请
    Encryption circuit 审中-公开
    加密电路

    公开(公告)号：US20050271201A1

    公开(公告)日：2005-12-08

    申请号：US11133289

    申请日：2005-05-20

    申请人： Kazuya Shimizu ,  Tomoya Sato ,  Kentaro Shiomi ,  Yusuke Nemoto ,  Yuishi Torisaki ,  Makoto Fujiwara

    发明人： Kazuya Shimizu ,  Tomoya Sato ,  Kentaro Shiomi ,  Yusuke Nemoto ,  Yuishi Torisaki ,  Makoto Fujiwara

    IPC分类号： H04L9/10 ,  G06K19/073 ,  H04K1/00 ,  H04L9/06

    CPC分类号： H04L9/0625 ,  H04L9/004 ,  H04L2209/12

    摘要： An encryption circuit of a secret key cryptosystem which inputs a plain text and a secret key 4A, inputs R partial keys Kn obtained from the secret key 4A and applies repeatedly R times of round operations to the plain text so that the plain text is encrypted including: registers 4G and 4H which store the values after the round operations of the plain text; a fault detection circuit 1A which decides whether a degenerate fault exists or not by the values of the registers 4G and 4H; and a circuit 1B which invalidates the secret key 4A when the degenerate fault exists in the detection result. The invention provides an encryption circuit which can appropriately respond to a new element of causing occurrence of the degenerate fault, suppress the cost of the hardware, and has a measure against the fault analysis while suppressing an increase in an encryption processing time.

    摘要翻译： 输入明文和秘密密钥4A的秘密密钥密码系统的加密电路输入从秘密密钥4A获得的R个部分密钥Kn，并且对明文重复地应用R次循环操作，使得明文是 加密包括：寄存器4G和4H，其在明文的循环操作之后存储值; 故障检测电路1A，其通过寄存器4G和4H的值判定退化故障是否存在; 以及当检测结果中存在退化故障时使秘密密钥4A无效的电路1B。 本发明提供了一种加密电路，其可以适当地响应引起退化故障的发生的新元件，抑制硬件的成本，并且在抑制加密处理时间的增加的同时具有针对故障分析的措施。

    Bus structure, database and method of designing interface
    18.
    发明申请
    Bus structure, database and method of designing interface 审中-公开

    公开(公告)号：US20050246667A1

    公开(公告)日：2005-11-03

    申请号：US11172905

    申请日：2005-07-05

    申请人： Makoto Fujiwara

    发明人： Makoto Fujiwara

    IPC分类号： G06F3/00 ,  G06F9/45 ,  G06F13/10 ,  G06F13/14 ,  G06F13/36 ,  G06F13/38 ,  G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

    CPC分类号： G06F17/5045

    摘要： With respect to each application, libraries, corresponding to operation models, for describing operations respectively attained by employing a Neumann CPU (bus structure), a Harvard CPU (bus structure) and a direction separate type CPU (bus structure) are registered. In a performance table of each library, the performance index of the library is expressed as a function of parameters of throughput, a bus width, instruction quantity and memory size. Also, a portion of the operation realized by using software and a portion realized by using hardware are registered. Through operation simulation conducted with each application successively replaced with each of the libraries, the performance of a semiconductor integrated circuit can be evaluated, so as to synthesize an optimal interface.

    Method for designing integrated circuit device
    19.
    发明授权
    Method for designing integrated circuit device 失效
    集成电路设备的设计方法

    公开(公告)号：US06886150B2

    公开(公告)日：2005-04-26

    申请号：US10067820

    申请日：2002-02-08

    申请人： Makoto Fujiwara ,  Akira Motohara ,  Toshiyuki Yokoyama

    发明人： Makoto Fujiwara ,  Akira Motohara ,  Toshiyuki Yokoyama

    IPC分类号： H01L21/82 ,  G06F17/50

    CPC分类号： G06F17/5045

    摘要： Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable resource information and the inter-block exclusive operation information, a resource sharable among the blocks is extracted. Module specifications, in which information about interfaces, power dissipation, operation models and top-level hierarchy interconnection is stored, exclusive operation information describing an exclusive operation rule among the blocks, and prioritized function information used for preventing respective functions from being enabled at the same time are input to an generator, which is an automatic generating tool. In this manner, a power and clock management module for use in power save management, a wrapper bank select module storing interconnection information, a shared resource module storing information about a sharable resource and an optimized top-level hierarchy module storing interconnection information about an optimized top-level hierarchy are generated. Downsizing and power saving are realized by resource sharing and power management.

    摘要翻译： 关于多个块中的排他性操作的信息和关于每个这些块内的可共享资源的互连信息被定义。 基于可共享资源信息和块间专用操作信息，提取在块之间可共享的资源。 存储关于接口，功耗，操作模型和顶级层级互连的信息的模块规格，描述块之间的排他性操作规则的排他性操作信息，以及用于防止各功能在相同功能中被使能的优先功能信息 时间被输入到作为自动生成工具的发电机。 以这种方式，用于节电管理的电源和时钟管理模块，存储互连信息的封装器组选择模块，存储关于可共享资源的信息的共享资源模块和存储关于优化的互连信息的优化顶层层级模块 生成顶级层次结构。 资源共享和电源管理实现了小型化和省电化。