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    Apparatus and Method for Reconstructing a Bit Sequence with Preliminary Correction
    11.
    发明申请
    Apparatus and Method for Reconstructing a Bit Sequence with Preliminary Correction 有权
    用初步校正重构位序列的装置和方法

    公开(公告)号：US20130246881A1

    公开(公告)日：2013-09-19

    申请号：US13803324

    申请日：2013-03-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Rainer Goettfert ,  Gerd Dirscherl ,  Berndt Gammel ,  Thomas Kuenemund

    IPC: H03M13/00

    CPC classification number: H03M13/00 ,  H03M13/03 ,  H03M13/3707 ,  H04L1/0045 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/34

    Abstract: A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF At and performing a preliminary correction of the potentially erroneous PUF At by means of a stored correction vector Deltat-1, to obtain a preliminarily corrected PUF Bt. The PUF A is reconstructed from the preliminarily corrected PUF Bt by means of an error correction algorithm. A corresponding apparatus is also provided.

    Abstract translation: 提供了用于重建用于电子设备的物理上不可克隆功能（PUF）A的方法。 该方法包括产生潜在错误的PUF At，并通过存储的校正矢量Deltat-1对潜在错误的PUF At进行初步校正，以获得预先校正的PUF Bt。 通过纠错算法从预先校正的PUF Bt重建PUF A。 还提供了相应的装置。

    Data processing arrangement and method for data processing
    15.
    发明授权
    Data processing arrangement and method for data processing 有权

    公开(公告)号：US09652232B2

    公开(公告)日：2017-05-16

    申请号：US14341925

    申请日：2014-07-28

    Applicant: Infineon Technologies AG

    Inventor： Rainer Goettfert ,  Berndt Gammel ,  Gerd Dirscherl

    IPC: G06F9/30 ,  G06F9/38 ,  G06F21/85

    CPC classification number: G06F9/3004 ,  G06F9/3885 ,  G06F21/85

    Abstract: A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.

    Integrated Circuit for Generating Random Vectors
    16.
    发明公开
    Integrated Circuit for Generating Random Vectors 审中-公开

    公开(公告)号：US20230244450A1

    公开(公告)日：2023-08-03

    申请号：US18104550

    申请日：2023-02-01

    Applicant: Infineon Technologies AG

    Inventor： Rainer Göettfert ,  Gerd Dirscherl ,  Berndt Gammel

    IPC: G06F7/58 ,  G06F17/16

    CPC classification number: G06F7/588 ,  G06F17/16

    Abstract: According to one exemplary embodiment, an integrated circuit is described, comprising multiple noise sources, each noise source being configured to output a respective set of noise bits for a random vector, a combinational logic circuit configured to process a noise bit vector, corresponding to a concatenation of the bits of the sets of noise bits, in accordance with a multiplication by a matrix to produce a processed noise bit vector, with the result that the processed noise bit vector comprises more bits than each of the sets of noise bits and comprises fewer bits than the noise bit vector; and a post-processing logic circuit configured to generate the random vector from the processed noise bit vector.

    METHOD FOR DETERMINING AN INTERGRITY OF AN EXECUTION OF A CODE FRAGMENT AND A METHOD FOR PROVIDING AN ABSTRACTED REPRESENTATION OF A PROGRAM CODE
    18.
    发明申请
    METHOD FOR DETERMINING AN INTERGRITY OF AN EXECUTION OF A CODE FRAGMENT AND A METHOD FOR PROVIDING AN ABSTRACTED REPRESENTATION OF A PROGRAM CODE 审中-公开
    确定代码片段执行的一致性的方法和提供程序代码的摘要表示的方法

    公开(公告)号：US20170024304A1

    公开(公告)日：2017-01-26

    申请号：US15214045

    申请日：2016-07-19

    Applicant: Infineon Technologies AG

    Inventor： Gerd Dirscherl ,  Marcel Schaible ,  Michael Smola ,  Bernhard Sommer

    IPC: G06F11/36

    CPC classification number: G06F11/28

    Abstract: A method for determining an integrity of an execution of a code fragment is provided. The method includes identifying a reference signature for the code fragment within an abstracted representation of a program code comprising the code fragment. Further, the method includes executing the code fragment and determining a signature of the executed code fragment. The method includes comparing the signature with the reference signature.

    Abstract translation: 提供了一种用于确定代码片段的执行的完整性的方法。 该方法包括在包含代码片段的程序代码的抽象表示中识别代码片段的参考签名。 此外，该方法包括执行代码片段并确定所执行的代码片段的签名。 该方法包括将签名与参考签名进行比较。

    System on chip with embedded security module
    19.
    发明授权
    System on chip with embedded security module 有权
    带嵌入式安全模块的片上系统

    公开(公告)号：US09471793B2

    公开(公告)日：2016-10-18

    申请号：US14137065

    申请日：2013-12-20

    Applicant: Infineon Technologies AG

    Inventor： Markus Gail ,  Gerd Dirscherl ,  Marcus Janke

    IPC: G06F7/04 ,  G06F21/60 ,  G06F21/00 ,  G06F21/71

    CPC classification number: G06F21/60 ,  G06F21/00 ,  G06F21/71 ,  G06F2221/2121

    Abstract: An embedded security module includes a security processor, volatile and non-volatile memory, and an interface. The security processor includes transistors formed in one or more semiconductor layers of a semiconductor die, and implements one or more security-related functions on data and/or code accessed by the security processor. The volatile memory is fabricated on the same semiconductor die as the security processor and stores the data and/or code accessed by the security processor. The non-volatile memory includes non-volatile storage cells disposed above each semiconductor layer of the semiconductor die, and securely stores at least one of the data and/or code accessed by the security processor and security information relating to the data and/or code accessed by the security processor. The interface is fabricated on the same semiconductor die as the security processor and provides a communication interface for the security processor.

    Abstract translation: 嵌入式安全模块包括安全处理器，易失性和非易失性存储器以及接口。 安全处理器包括形成在半导体管芯的一个或多个半导体层中的晶体管，并且对由安全处理器访问的数据和/或代码实现一个或多个与安全相关的功能。 易失性存储器被制造在与安全处理器相同的半导体管芯上，并存储由安全处理器访问的数据和/或代码。 非易失性存储器包括设置在半导体芯片的每个半导体层之上的非易失性存储单元，并且安全地存储由安全处理器访问的数据和/或代码中的至少一个以及与数据和/或代码相关的安全信息 由安全处理器访问。 该接口在与安全处理器相同的半导体管芯上制造，并为安全处理器提供通信接口。

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