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    PULSE AMPLITUDE MODULATION (PAM) DATA COMMUNICATION WITH FORWARD ERROR CORRECTION
    13.
    发明申请
    PULSE AMPLITUDE MODULATION (PAM) DATA COMMUNICATION WITH FORWARD ERROR CORRECTION 有权

    公开(公告)号：US20170187555A1

    公开(公告)日：2017-06-29

    申请号：US15405020

    申请日：2017-01-12

    Applicant: INPHI CORPORATION

    Inventor： Arun TIRUVUR ,  Jamal RIANI ,  Sudeep BHOJA

    IPC: H04L27/04 ,  H04L1/00

    CPC classification number: H04L27/04 ,  H04L1/0041 ,  H04L1/0042 ,  H04L1/0045 ,  H04L25/14

    Abstract: The present invention is directed to data communication system and methods. More specifically, embodiments of the present invention provide an apparatus that receives data from multiple lanes, which are then synchronized for transcoding and encoding. A pseudo random bit sequence checker may be coupled to each of the plurality of lanes, which is configured to a first clock signal A. Additionally, an apparatus may include a plurality of skew compensator modules. Each of the skew compensator modules may be coupled to at least one of the plurality of lanes. The skew-compensator modules are configured to synchronize data from the plurality of lanes. The apparatus additionally includes a plurality of de-skew FIFO modules. Each of the de-skew compensator modules may be coupled to at least one of the plurality of skew compensator modules.

    SYSTEMS AND METHODS FOR TIMING RECOVERY WITH BANDWIDTH EXTENSION
    15.
    发明申请
    SYSTEMS AND METHODS FOR TIMING RECOVERY WITH BANDWIDTH EXTENSION 有权

    公开(公告)号：US20210336761A1

    公开(公告)日：2021-10-28

    申请号：US16860403

    申请日：2020-04-28

    Applicant: INPHI CORPORATION

    Inventor： Benjamin P. SMITH ,  Jamal RIANI

    IPC: H04L7/00 ,  H04L1/20

    Abstract: The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.

    METHOD AND DEVICE FOR DIGITAL COMPENSATION OF DYNAMIC DISTORTION IN HIGH-SPEED TRANSMITTERS
    17.
    发明申请
    METHOD AND DEVICE FOR DIGITAL COMPENSATION OF DYNAMIC DISTORTION IN HIGH-SPEED TRANSMITTERS 有权

    公开(公告)号：US20210297294A1

    公开(公告)日：2021-09-23

    申请号：US17224835

    申请日：2021-04-07

    Applicant: INPHI CORPORATION

    Inventor： Dragos CARTINA ,  Ankit BHARGAV ,  Jamal RIANI ,  Wen-Sin LIEW ,  Yu LIAO ,  Chang-Feng LOI

    IPC: H04L25/03 ,  H04L25/02 ,  H04L25/49 ,  G01R19/25 ,  G01R13/34 ,  H03F1/32

    Abstract: A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.

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