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公开(公告)号：US20160134394A1
公开(公告)日：2016-05-12
申请号：US14536303
申请日：2014-11-07
Applicant: INPHI CORPORATION
Inventor： Arun TIRUVUR , Sudeep BHOJA
CPC classification number: H04L25/03 , H04L1/004 , H04L1/0061 , H04L5/0048 , H04L25/03057 , H04L25/03885 , H04L25/4917 , H04L27/04 , H04L27/06 , H04L2025/03636 , H04Q11/0062 , H04Q2011/0088
Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.
Abstract translation: 本发明涉及数据通信系统和方法。 更具体地，本发明的实施例提供了用于收发机快速识别在数据通信中使用的FEC模式的技术。 发送收发器将FEC模式信息嵌入到对准标记的指定字段中。 接收收发器确认接收到FEC模式信息并相应地处理输入数据。 还有其它实施例。
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公开(公告)号：US20200099453A1
公开(公告)日：2020-03-26
申请号：US16696913
申请日：2019-11-26
Applicant: INPHI CORPORATION
Inventor： Karthik GOPALAKRISHNAN , Jamal RIANI , Arun TIRUVUR
IPC: H04B10/40 , H03K5/00 , H03K19/0185 , H03L7/093 , H03L7/099 , H03L7/197 , H03L7/23 , H04L7/00 , H04L25/00 , H04L25/49 , H04B10/54 , H04L7/033
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
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公开(公告)号：US20170187555A1
公开(公告)日：2017-06-29
申请号：US15405020
申请日：2017-01-12
Applicant: INPHI CORPORATION
Inventor： Arun TIRUVUR , Jamal RIANI , Sudeep BHOJA
CPC classification number: H04L27/04 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L25/14
Abstract: The present invention is directed to data communication system and methods. More specifically, embodiments of the present invention provide an apparatus that receives data from multiple lanes, which are then synchronized for transcoding and encoding. A pseudo random bit sequence checker may be coupled to each of the plurality of lanes, which is configured to a first clock signal A. Additionally, an apparatus may include a plurality of skew compensator modules. Each of the skew compensator modules may be coupled to at least one of the plurality of lanes. The skew-compensator modules are configured to synchronize data from the plurality of lanes. The apparatus additionally includes a plurality of de-skew FIFO modules. Each of the de-skew compensator modules may be coupled to at least one of the plurality of skew compensator modules.
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公开(公告)号：US20200052937A1
公开(公告)日：2020-02-13
申请号：US16657274
申请日：2019-10-18
Applicant: INPHI CORPORATION
Inventor： Arun TIRUVUR , Jamal RIANI , Sudeep BHOJA
Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.
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公开(公告)号：US20180248717A1
公开(公告)日：2018-08-30
申请号：US15968614
申请日：2018-05-01
Applicant: INPHI CORPORATION
Inventor： Arun TIRUVUR , Sudeep BHOJA
CPC classification number: H04L25/03 , H04L1/004 , H04L1/0061 , H04L5/0048 , H04L25/03057 , H04L25/03885 , H04L25/4917 , H04L27/04 , H04L27/06 , H04L2025/03636 , H04Q11/0062 , H04Q2011/0088
Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.
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Patent Agency Ranking
公开(公告)号：US20210167858A1
公开(公告)日：2021-06-03
申请号：US17171801
申请日：2021-02-09
Applicant: INPHI CORPORATION
Inventor： Karthik GOPALAKRISHNAN , Jamal RIANI , Arun TIRUVUR
IPC: H04B10/40 , H03K5/00 , H03K19/0185 , H03L7/093 , H03L7/099 , H03L7/197 , H03L7/23 , H04L7/00 , H04L25/00 , H04L25/49 , H04B10/54 , H04L7/033
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
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公开(公告)号：US20190149238A1
公开(公告)日：2019-05-16
申请号：US16249642
申请日：2019-01-16
Applicant: INPHI CORPORATION
Inventor： Karthik GOPALAKRISHNAN , Jamal RIANI , Arun TIRUVUR
IPC: H04B10/40 , H04L25/00 , H04L25/49 , H04L7/033 , H04L7/00 , H03L7/23 , H03L7/197 , H03L7/099 , H03L7/093 , H03K19/0185 , H03K5/00 , H04B10/54
CPC classification number: H04B10/40 , H03K5/00 , H03K19/018521 , H03L7/093 , H03L7/099 , H03L7/1976 , H03L7/23 , H03L2207/06 , H04B10/541 , H04L7/0037 , H04L7/0062 , H04L7/0079 , H04L7/0087 , H04L7/0091 , H04L7/0331 , H04L25/00 , H04L25/49
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
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公开(公告)号：US20180343151A1
公开(公告)日：2018-11-29
申请号：US15986085
申请日：2018-05-22
Applicant: INPHI CORPORATION
Inventor： Arun TIRUVUR , Jamal RIANI , Sudeep BHOJA
Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.
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公开(公告)号：US20180131443A1
公开(公告)日：2018-05-10
申请号：US15809902
申请日：2017-11-10
Applicant: INPHI CORPORATION
Inventor： Karthik Gopalakrishnan , Jamal RIANI , Arun TIRUVUR
CPC classification number: H04B10/40 , H03K5/00 , H03K19/018521 , H03L7/093 , H03L7/099 , H03L7/1976 , H03L7/23 , H03L2207/06 , H04B10/541 , H04L7/0037 , H04L7/0062 , H04L7/0079 , H04L7/0087 , H04L7/0091 , H04L7/0331 , H04L25/00
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
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公开(公告)号：US20170207933A1
公开(公告)日：2017-07-20
申请号：US15476323
申请日：2017-03-31
Applicant: INPHI CORPORATION
Inventor： Arun TIRUVUR , Sudeep BHOJA
CPC classification number: H04L25/03 , H04L1/004 , H04L1/0061 , H04L5/0048 , H04L25/03057 , H04L25/03885 , H04L25/4917 , H04L27/04 , H04L27/06 , H04L2025/03636 , H04Q11/0062 , H04Q2011/0088
Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.
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