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    Techniques for control flow protection
    12.
    发明授权
    Techniques for control flow protection 有权

    公开(公告)号：US11347839B2

    公开(公告)日：2022-05-31

    申请号：US16452916

    申请日：2019-06-26

    Applicant: INTEL CORPORATION

    Inventor： Abhishek Basak ,  Ravi L. Sahita ,  Vedvyas Shanbhogue

    IPC: G06F21/00 ,  G06F21/52 ,  G06F12/126 ,  G06F12/06

    Abstract: Various embodiments are generally directed to techniques for control flow protection with minimal performance overhead, such as by utilizing one or more micro-architectural optimizations to implement a shadow stack (SS) to verify a return address before returning from a function call, for instance. Some embodiments are particularly directed to a computing platform, such as an internet of things (IoT) platform, that overlaps or parallelizes one or more SS access operations with one or more data stack (DS) access operations.

    HARDENING CPU PREDICTORS WITH CRYPTOGRAPHIC COMPUTING CONTEXT INFORMATION
    13.
    发明申请
    HARDENING CPU PREDICTORS WITH CRYPTOGRAPHIC COMPUTING CONTEXT INFORMATION 有权

    公开(公告)号：US20220121447A1

    公开(公告)日：2022-04-21

    申请号：US17560363

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Abhishek Basak ,  Santosh Ghosh ,  Michael D. LeMay ,  David M. Durham

    IPC: G06F9/38 ,  G06F9/30

    Abstract: In one embodiment, a processor includes a memory hierarchy and a core. The core includes circuitry to access an encoded code pointer for a load instruction and perform a memory disambiguation (MD) lookup using a subset of address bits indicated by the encoded code pointer and context information indicated by one or more of the encoded code pointer or an encoded data pointer of the load instruction. The circuitry is further to determine, based on the MD lookup, that the load instruction is predicted to be independent from previous store instructions and forward the load instruction for out-of-order execution based on the determination.

    Technologies for filtering memory access transactions received from one or more I/O devices
    15.
    发明授权
    Technologies for filtering memory access transactions received from one or more I/O devices 有权

    公开(公告)号：US11163913B2

    公开(公告)日：2021-11-02

    申请号：US16234871

    申请日：2018-12-28

    Applicant: Intel Corporation

    Inventor： Luis Kida ,  Krystof Zmudzinski ,  Reshma Lal ,  Pradeep Pappachan ,  Abhishek Basak ,  Anna Trikalinou

    IPC: G06F21/78 ,  G06F21/44 ,  G06F21/85

    Abstract: Technologies for secure I/O include a compute device having a processor, a memory, an input/output (I/O) device, and a filter logic. The filter logic is configured to receive a first key identifier from the processor, wherein the first key identifier is indicative of a shared memory range includes a shared key identifier range to be used for untrusted I/O devices and receive a transaction from the I/O device, wherein the transaction includes a second key identifier and a trust device ID indicator associated with the I/O device. The filter logic is further configured to determine whether the transaction is asserted with the trust device ID indicator indicative of whether the I/O device is assigned to a trust domain and determine, in response to a determination that the transaction is not asserted with the trust device ID indicator, whether the second key identifier matches the first key identifier.

    Hardware based technique to prevent critical fine-grained cache side-channel attacks
    16.
    发明授权
    Hardware based technique to prevent critical fine-grained cache side-channel attacks 有权

    公开(公告)号：US11144468B2

    公开(公告)日：2021-10-12

    申请号：US16024072

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Abhishek Basak ,  Arun Kanuparthi ,  Nagaraju N. Kodalapura ,  Jason M. Fung

    IPC: G06F12/0891

    Abstract: A system may include a processor and a memory, the processor having at least one cache. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line may include several bits for storing information, including at least a “shared” bit to indicate whether the cache line is shared between different processes being executed by the processor. The example cache may also include shared cache line detection and eviction logic. During normal operation, the cache logic may monitor for a context switch (i.e., determine if the processor is switching from executing instructions for a first process to executing instructions for a second process). Upon a context switch, the cache logic may evict the shared cache lines (e.g., the cache lines with a shared bit of 1). This eviction of shared cache lines may prevent attackers utilizing such attacks from gleaning meaningful information.

    HEURISTIC AND MACHINE-LEARNING BASED METHODS TO PREVENT FINE-GRAINED CACHE SIDE-CHANNEL ATTACKS
    18.
    发明申请
    HEURISTIC AND MACHINE-LEARNING BASED METHODS TO PREVENT FINE-GRAINED CACHE SIDE-CHANNEL ATTACKS 审中-公开

    公开(公告)号：US20190042479A1

    公开(公告)日：2019-02-07

    申请号：US16024198

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Abhishek Basak ,  Li Chen ,  Ravi Sahita

    IPC: G06F12/14 ,  G06F12/0891 ,  G06F21/55

    Abstract: A system may include a processor and a memory, the processor having at least one cache as well as memory access monitoring logic. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line includes several bits for storing information. During normal operation, the memory access monitoring logic may monitor for a memory access pattern indicative of a side-channel attack (e.g., an abnormally large number of recent CLFLUSH instructions). Upon detecting a possible side-channel attack, the memory access monitoring logic may implement one of several mitigation policies, such as, for example, restricting execution of CLFLUSH operations. Due to the nature of cache-timing side-channel attacks, this prevention of CLFLUSH may prevent attackers utilizing such attacks from gleaning meaningful information.

    Cryptographic computing with legacy peripheral devices
    19.
    发明授权
    Cryptographic computing with legacy peripheral devices 有权

    公开(公告)号：US12210660B2

    公开(公告)日：2025-01-28

    申请号：US17548170

    申请日：2021-12-10

    Applicant: Intel Corporation

    Inventor： Anna Trikalinou ,  Abhishek Basak ,  Rupin H. Vakharwala ,  Utkarsh Y. Kakaiya

    IPC: G06F21/83 ,  G06F21/62 ,  G06F21/78

    Abstract: In one embodiment, a read request is received from a peripheral device across an interconnect, with the read request including a process identifier and an encrypted virtual address. One or more keys are obtained based on the process identifier of the read request, and the encrypted virtual address of the read request is decrypted based on the one or more keys to obtain an unencrypted virtual address. Encrypted data is retrieved from memory based on the unencrypted virtual address, and the encrypted data is decrypted based on the one or more keys to obtain plaintext data. The plaintext data is transmitted to the peripheral device across the interconnect.

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