公开(公告)号：US11675594B2

公开(公告)日：2023-06-13

申请号：US16236049

申请日：2018-12-28

申请人： Intel Corporation

发明人： Robert S. Chappell ,  Jason W. Brandt ,  Alan Cox ,  Asit Mallick ,  Joseph Nuzman ,  Arjan Van De Ven

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F21/55

CPC分类号： G06F9/3842 ,  G06F9/30058 ,  G06F9/30145 ,  G06F21/556 ,  G06F2221/033

摘要： Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

公开(公告)号：US20220207147A1

公开(公告)日：2022-06-30

申请号：US17134343

申请日：2020-12-26

申请人： Intel Corporation

发明人： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC分类号： G06F21/57 ,  G06F21/54 ,  G06F9/30

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.

公开(公告)号：US20160004533A1

公开(公告)日：2016-01-07

申请号：US14854082

申请日：2015-09-15

申请人： INTEL CORPORATION

发明人： Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

IPC分类号： G06F9/30 ,  G06F1/32

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3265 ,  G06F1/3268 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/461 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/154 ,  Y02D10/172 ,  Y02D50/20

摘要： Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.

摘要翻译： 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。

公开(公告)号：US20220207138A1

公开(公告)日：2022-06-30

申请号：US17134350

申请日：2020-12-26

申请人： Intel Corporation

发明人： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC分类号： G06F21/55 ,  G06F21/54 ,  G06F9/30 ,  G06F9/38

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.

公开(公告)号：US09898330B2

公开(公告)日：2018-02-20

申请号：US14076341

申请日：2013-11-11

申请人： Intel Corporation

发明人： Atul Khare ,  Leena Puthiyedath ,  Asit Mallick ,  Jim Coke ,  Michael Mishaeli ,  Gilbert Neiger ,  Vivekananthan Sanjeepan ,  Jason Brandt

IPC分类号： G06F9/46 ,  G06F9/30

CPC分类号： G06F9/461 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101

摘要： Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

公开(公告)号：US09600283B2

公开(公告)日：2017-03-21

申请号：US14854082

申请日：2015-09-15

申请人： INTEL CORPORATION

发明人： Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

IPC分类号： G06F9/30 ,  G06F1/32 ,  G06F9/46

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3265 ,  G06F1/3268 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/461 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/154 ,  Y02D10/172 ,  Y02D50/20

摘要： Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.

公开(公告)号：US20240338238A1

公开(公告)日：2024-10-10

申请号：US18574849

申请日：2022-01-26

申请人： Intel Corporation

发明人： Wei Wang ,  Kun Tian ,  Guang Zeng ,  Gilbert Neiger ,  Rajesh Sankaran ,  Asit Mallick ,  Jr-Shian Tsai ,  Jacob Jun Pan ,  Mesut Ergin

IPC分类号： G06F9/455 ,  G06F9/30

CPC分类号： G06F9/45558 ,  G06F9/3016 ,  G06F9/45545 ,  G06F2009/45579

摘要： A method and system of host to guest (H2G) notification are disclosed. H2G is provided via an instruction. The instruction is a send user inter-processor interrupt instruction. An exemplary processor includes decoder circuitry to decode a single instruction and execute the decoded single instruction according to the at least the opcode to cause a host to guest notification from a virtual device running in a host machine on the first physical processor to a virtual device driver running on a virtual processor in a guest machine on a second physical processor.

公开(公告)号：US10120805B2

公开(公告)日：2018-11-06

申请号：US15408774

申请日：2017-01-18

申请人： Intel Corporation

发明人： Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Carlos V. Rozas ,  Gilbert Neiger ,  Asit Mallick ,  Ittai Anati ,  Ilya Alexandrovich ,  Vedvyas Shanbhogue ,  Somnath Chakrabarti

IPC分类号： G06F9/30 ,  G06F12/0837 ,  G06F9/455 ,  G06F12/1045

摘要： A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.

公开(公告)号：US20180203801A1

公开(公告)日：2018-07-19

申请号：US15408774

申请日：2017-01-18

申请人： Intel Corporation

发明人： Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Carlos V. Rozas ,  Gilbert Neiger ,  Asit Mallick ,  Ittai Anati ,  Ilya Alexandrovich ,  Vedvyas Shanbhogue ,  Somnath Chakrabarti

IPC分类号： G06F12/0837 ,  G06F9/30 ,  G06F9/455 ,  G06F12/1045

CPC分类号： G06F12/0837 ,  G06F9/30003 ,  G06F9/45558 ,  G06F12/1063 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/152 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/68

摘要： A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.

公开(公告)号：US20180060237A1

公开(公告)日：2018-03-01

申请号：US15252719

申请日：2016-08-31

申请人： Intel Corporation

发明人： Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Carlos V. Rozas ,  Somnath Chakrabarti ,  Asit Mallick

IPC分类号： G06F12/0817 ,  G06F21/57 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084

CPC分类号： G06F12/0824 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F21/53 ,  G06F21/572 ,  G06F2212/1008 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2221/032

摘要： A processing device includes a first counter having a first count value of a number of child pages among a plurality of child pages present in an enclave memory of a first virtual machine (VM). The plurality of child pages are associated with a parent page in the enclave memory. The processing device includes a second counter having a second count value of a number of child pages among the plurality of child pages not present in the enclave memory and being shared by a second VM, wherein the second VM is different from the first VM. A non-zero value of at least one of the first counter or the second counter prevents eviction of the parent page from the enclave memory.