公开(公告)号：US20220173090A1

公开(公告)日：2022-06-02

申请号：US17210836

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Van H. Le ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.

公开(公告)号：US20220173046A1

公开(公告)日：2022-06-02

申请号：US17210682

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Abhishek A. Sharma ,  Doug B. Ingerly ,  Mauro J. Kobrinsky ,  Kevin Fischer

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/12

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

公开(公告)号：US12278229B2

公开(公告)日：2025-04-15

申请号：US18474275

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US20220399310A1

公开(公告)日：2022-12-15

申请号：US17345369

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Mauro J. Kobrinsky ,  Doug B. Ingerly ,  Van H. Le

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

公开(公告)号：US20220181256A1

公开(公告)日：2022-06-09

申请号：US17114537

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Mauro J. Kobrinsky ,  Doug B. Ingerly

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/18 ,  H01L23/48

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

公开(公告)号：US20210407932A1

公开(公告)日：2021-12-30

申请号：US16914045

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Mohammad Kabir ,  Conor P. Puls ,  Babita Dhayal ,  Han Li ,  Keith E. Zawadzki ,  Hannes Greve ,  Avyaya Jayanthinarasimham ,  Mukund Bapna ,  Doug B. Ingerly

IPC: H01L23/00 ,  H01L27/12 ,  H01L23/58 ,  H01L21/762

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

公开(公告)号：US10886195B2

公开(公告)日：2021-01-05

申请号：US16316504

申请日：2016-08-18

Applicant: INTEL CORPORATION

Inventor： Doug B. Ingerly ,  Candi S. Cook

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor structure is described. The semiconductor structure includes a semiconductor substrate and a through-silicon via (TSV). The TSV is disposed between a first surface of the semiconductor substrate and an interconnection layer disposed on a second surface of the semiconductor substrate, where the first surface of the semiconductor substrate is opposite to the second surface. The TSV has an external surface that interfaces with the semiconductor substrate. In one embodiment, the external surface includes a protrusion that extends into the semiconductor substrate. In another embodiment, the TSV includes one or more voids. In yet another embodiment, the TSV includes both protrusions and voids. The protrusions and/or the one or more voids may reduce thermal expansion stress. Other embodiments may be described and/or claimed.

公开(公告)号：US20190311973A1

公开(公告)日：2019-10-10

申请号：US16316504

申请日：2016-08-18

Applicant: INTEL CORPORATION

Inventor： Doug B. Ingerly ,  Candi S. Cook

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768

Abstract: A semiconductor structure is described. The semiconductor structure includes a semiconductor substrate and a through-silicon via (TSV). The TSV is disposed between a first surface of the semiconductor substrate and an interconnection layer disposed on a second surface of the semiconductor substrate, where the first surface of the semiconductor substrate is opposite to the second surface. The TSV has an external surface that interfaces with the semiconductor substrate. In one embodiment, the external surface includes a protrusion that extends into the semiconductor substrate. In another embodiment, the TSV includes one or more voids. In yet another embodiment, the TSV includes both protrusions and voids. The protrusions and/or the one or more voids may reduce thermal expansion stress. Other embodiments may be described and/or claimed.