公开(公告)号：US12166031B2

公开(公告)日：2024-12-10

申请号：US17131616

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Brian Greene ,  Daniel Schulman ,  William Hsu ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/87

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

公开(公告)号：US11239238B2

公开(公告)日：2022-02-01

申请号：US16667740

申请日：2019-10-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Conor P. Puls ,  Kevin Fischer ,  Bernhard Sell ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L29/24 ,  H01L49/02 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US12170273B2

公开(公告)日：2024-12-17

申请号：US17210682

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Abhishek A. Sharma ,  Doug B. Ingerly ,  Mauro J. Kobrinsky ,  Kevin Fischer

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/12 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

公开(公告)号：US11690211B2

公开(公告)日：2023-06-27

申请号：US17511646

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Conor P. Puls ,  Kevin Fischer ,  Bernhard Sell ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L29/24 ,  H01L49/02 ,  H01L29/786 ,  H01L29/66 ,  H10B10/00

CPC classification number: H10B12/30 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/32 ,  H01L24/83 ,  H01L28/60 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78681 ,  H10B12/05 ,  H10B12/50 ,  H01L2224/32225 ,  H01L2924/1436 ,  H01L2924/1437 ,  H10B10/12

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20220173046A1

公开(公告)日：2022-06-02

申请号：US17210682

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Sanka Ganesan ,  Abhishek A. Sharma ,  Doug B. Ingerly ,  Mauro J. Kobrinsky ,  Kevin Fischer

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/12

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

公开(公告)号：US20210408289A1

公开(公告)日：2021-12-30

申请号：US16914145

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Brian Greene ,  Robin Chao ,  Adam Faust ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

公开(公告)号：US20210125990A1

公开(公告)日：2021-04-29

申请号：US16667740

申请日：2019-10-29

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Conor P. Puls ,  Kevin Fischer ,  Bernhard Sell ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L29/24 ,  H01L49/02 ,  H01L29/786 ,  H01L29/66

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.