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    SMS4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    11.
    发明申请
    SMS4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 有权
    SMS4加速处理器，方法，系统和指令

    公开(公告)号：US20150186138A1

    公开(公告)日：2015-07-02

    申请号：US14142724

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: G06F9/30 ,  G06F21/60

    CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3895 ,  G06F21/602 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

    Abstract: A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SMS4 rounds. The one or more source operands are also to have a 32-bit value. An execution unit is coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store a 32-bit result of a current SMS4 round in a destination storage location that is to be indicated by the instruction.

    Abstract translation: 一方面的处理器包括多个打包数据寄存器和用于解码指令的解码单元。 该指令是指示一个或多个源打包数据操作数。 一个或多个源打包数据操作数具有四个先前的SMS4回合的四个32位结果。 一个或多个源操作数也具有32位值。 执行单元与解码单元和多个打包数据寄存器耦合。 执行单元响应于该指令，将当前SMS4的32位结果存储在要由指令指示的目的地存储单元中。

    INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY
    13.
    发明申请
    INSTRUCTIONS AND LOGIC TO PROVIDE SIMD SM4 CRYPTOGRAPHIC BLOCK CIPHER FUNCTIONALITY 有权

    公开(公告)号：US20220353070A1

    公开(公告)日：2022-11-03

    申请号：US17718237

    申请日：2022-04-11

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

    Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

    Instructions and logic to provide SIMD SM3 cryptographic hashing functionality
    16.
    发明授权
    Instructions and logic to provide SIMD SM3 cryptographic hashing functionality 有权

    公开(公告)号：US10592245B2

    公开(公告)日：2020-03-17

    申请号：US15600200

    申请日：2017-05-19

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Sean M. Gulley ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: G06F9/30 ,  G06F21/72

    Abstract: Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.

    Hardware accelerators and methods for stateful compression and decompression operations
    20.
    发明授权
    Hardware accelerators and methods for stateful compression and decompression operations 有权

    公开(公告)号：US10169073B2

    公开(公告)日：2019-01-01

    申请号：US14975847

    申请日：2015-12-20

    Applicant: Intel Corporation

    Inventor： Tracy G. Drysdale ,  James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  James T. Kukunas

    IPC: G06F9/46 ,  G06F9/50

    Abstract: Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.

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