公开(公告)号：US10333379B2

公开(公告)日：2019-06-25

申请号：US15382076

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Suphachai Chai Sutanthavibul ,  Iqbal Rajwani ,  Anupama A Thaploo ,  Surya Sasi Kiran Tallapragada ,  Daivik H Bhatt ,  Lei Jiang ,  Stephen Kim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H02M1/08 ,  H03K17/0812 ,  H03K17/687 ,  H02M3/158 ,  H02M1/088 ,  H03K19/00 ,  H02M1/00 ,  H03K17/08

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

公开(公告)号：US20250061535A1

公开(公告)日：2025-02-20

申请号：US18820907

申请日：2024-08-30

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US12056789B2

公开(公告)日：2024-08-06

申请号：US18455128

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

CPC classification number: G06T1/20 ,  G06F13/4027

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US11763416B2

公开(公告)日：2023-09-19

申请号：US17500375

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

CPC classification number: G06T1/20 ,  G06F13/4027

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US20210064111A1

公开(公告)日：2021-03-04

申请号：US16994073

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/28

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US20200294180A1

公开(公告)日：2020-09-17

申请号：US16355303

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Josh Mastronarde ,  Naveen Matam ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

公开(公告)号：US20240013338A1

公开(公告)日：2024-01-11

申请号：US18470652

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

CPC classification number: G06T1/20 ,  G06F13/4027

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US11756150B2

公开(公告)日：2023-09-12

申请号：US17674781

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

CPC classification number: G06T1/20 ,  G06F13/4027

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US20230030396A1

公开(公告)日：2023-02-02

申请号：US17966151

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Iqbal Rajwani ,  Bhushan Borole ,  Kamal Sinha ,  Sanjeev Jahagirdar

IPC: G06F1/28

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

公开(公告)号：US20220188967A1

公开(公告)日：2022-06-16

申请号：US17685117

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Josh Mastronarde ,  Naveen Matam ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC: G06T1/20 ,  G06F13/40

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets, With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.