公开(公告)号：US20220180468A1

公开(公告)日：2022-06-09

申请号：US17674781

申请日：2022-02-17

申请人： Intel Corporation

发明人： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

摘要： Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US20210133913A1

公开(公告)日：2021-05-06

申请号：US17069188

申请日：2020-10-13

申请人： Intel Corporation

发明人： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

摘要： Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US20200294181A1

公开(公告)日：2020-09-17

申请号：US16355377

申请日：2019-03-15

申请人： Intel Corporation

发明人： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

摘要： Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US12056789B2

公开(公告)日：2024-08-06

申请号：US18455128

申请日：2023-08-24

申请人： Intel Corporation

发明人： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

CPC分类号： G06T1/20 ,  G06F13/4027

摘要： Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US20240061582A1

公开(公告)日：2024-02-22

申请号：US17820356

申请日：2022-08-17

申请人： Intel Corporation

发明人： Marc Beuchat ,  Eric Samson ,  Josh Mastronarde

IPC分类号： G06F3/06

CPC分类号： G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

摘要： Methods, systems and apparatuses provide for technology that detects an access to memory, wherein the memory is on a discrete graphics device that includes an accelerator, sets an idle hysteresis value of the memory to a first level if the access to the memory is associated with activity in the accelerator, and sets the idle hysteresis value of the memory to a second level if the access to the memory is not associated with the activity in the accelerator, wherein the second level is greater than the first level.

公开(公告)号：US11763416B2

公开(公告)日：2023-09-19

申请号：US17500375

申请日：2021-10-13

申请人： Intel Corporation

发明人： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

CPC分类号： G06T1/20 ,  G06F13/4027

摘要： Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US20200294180A1

公开(公告)日：2020-09-17

申请号：US16355303

申请日：2019-03-15

申请人： Intel Corporation

发明人： Altug Koker ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Josh Mastronarde ,  Naveen Matam ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

摘要： A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

公开(公告)号：US12079155B2

公开(公告)日：2024-09-03

申请号：US17428216

申请日：2020-03-14

申请人： Intel Corporation

发明人： Joydeep Ray ,  Selvakumar Panneer ,  Saurabh Tangri ,  Ben Ashbaugh ,  Scott Janus ,  Abhishek Appu ,  Varghese George ,  Ravishankar Iyer ,  Nilesh Jain ,  Pattabhiraman K ,  Altug Koker ,  Mike MacPherson ,  Josh Mastronarde ,  Elmoustapha Ould-Ahmed-Vall ,  Jayakrishna P. S ,  Eric Samson

IPC分类号： G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US20240013338A1

公开(公告)日：2024-01-11

申请号：US18470652

申请日：2023-09-20

申请人： Intel Corporation

发明人： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

CPC分类号： G06T1/20 ,  G06F13/4027

摘要： Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US11756150B2

公开(公告)日：2023-09-12

申请号：US17674781

申请日：2022-02-17

申请人： Intel Corporation

发明人： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

CPC分类号： G06T1/20 ,  G06F13/4027

摘要： Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.