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    Spatial and temporal merging of remote atomic operations
    11.
    发明授权
    Spatial and temporal merging of remote atomic operations 有权

    公开(公告)号：US10572260B2

    公开(公告)日：2020-02-25

    申请号：US15858899

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

    IPC: G06F9/30 ,  G06F12/0875

    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

    Remote atomic operations in multi-socket systems
    12.
    发明授权
    Remote atomic operations in multi-socket systems 有权

    公开(公告)号：US10296459B1

    公开(公告)日：2019-05-21

    申请号：US15858894

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  Christopher J. Hughes ,  Jonas Svennebring ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  David A. Koufaty

    IPC: G06F12/0831 ,  G06F12/0815 ,  G06F12/0808 ,  G06F9/30

    Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

    LINK PERFORMANCE PREDICTION USING SPATIAL LINK PERFORMANCE MAPPING
    14.
    发明公开
    LINK PERFORMANCE PREDICTION USING SPATIAL LINK PERFORMANCE MAPPING 审中-公开

    公开(公告)号：US20230308199A1

    公开(公告)日：2023-09-28

    申请号：US18023699

    申请日：2021-09-24

    Applicant: Intel Corporation

    Inventor： Jonas Svennebring ,  Theoharis Charitidis

    IPC: H04B17/391 ,  H04B17/373 ,  H04W16/22

    CPC classification number: H04B17/3913 ,  H04B17/373 ,  H04W16/22

    Abstract: In one embodiment, a current path of a mobile device is determined based on radio signals between the mobile device and a base station, which indicates a sequence of positions of the mobile device over a current time window. A future path of the mobile device is then predicted based on the current path, which indicates a sequence of predicted future positions of the mobile device over a future time window. A link performance prediction (LPP) is then generated for the mobile device based on the future path of the mobile device and a base station coverage map. The base station coverage map indicates a radio signal quality across a base station coverage area, which is represented as a three-dimensional (3D) coordinate space. Moreover, the LPP indicates a predicted performance of a radio link between the mobile device and the base station during the future time window.

    Link performance prediction technologies
    15.
    发明授权
    Link performance prediction technologies 有权

    公开(公告)号：US11711284B2

    公开(公告)日：2023-07-25

    申请号：US17505919

    申请日：2021-10-20

    Applicant: Intel Corporation

    Inventor： Jonas Svennebring ,  Antony Vance Jeyaraj

    IPC: H04L43/0882 ,  H04W24/08

    CPC classification number: H04L43/0882 ,  H04W24/08

    Abstract: Various systems and methods for determining and communicating Link Performance Predictions (LPPs), such as in connection with management of radio communication links, are discussed herein. The LPPs are predictions of future network behaviors/metrics (e.g., bandwidth, latency, capacity, coverage holes, etc.). The LPPs are communicated to applications and/or network infrastructure, which allows the applications/infrastructure to make operational decisions for improved signaling/link resource utilization. In embodiments, the link performance analysis is divided into multiple layers that determine their own link performance metrics, which are then fused together to make an LPP. Each layer runs different algorithms, and provides respective results to an LPP layer/engine that fuses the results together to obtain the LPP. Other embodiments are described and/or claimed.

    INSTRUCTIONS FOR REMOTE ATOMIC OPERATIONS
    20.
    发明申请
    INSTRUCTIONS FOR REMOTE ATOMIC OPERATIONS 审中-公开

    公开(公告)号：US20190004810A1

    公开(公告)日：2019-01-03

    申请号：US15638120

    申请日：2017-06-29

    Applicant: Intel Corporation

    Inventor： Doddaballapur N. Jayasimha ,  Jonas Svennebring ,  Samantika S. Sury ,  Christopher J. Hughes ,  Jong Soo Park ,  Lingxiang Xiang

    IPC: G06F9/38 ,  G06F12/0893 ,  G06F9/26 ,  G06F13/28

    Abstract: Disclosed embodiments relate to atomic memory operations. In one example, a method of executing an instruction atomically and with weak order includes: fetching, by fetch circuitry, the instruction from code storage, the instruction including an opcode, a source identifier, and a destination identifier, decoding, by decode circuitry, the fetched instruction, selecting, by a scheduling circuit, an execution circuit among multiple circuits in a system, scheduling, by the scheduling circuit, execution of the decoded instruction out of order with respect to other instructions, with an order selected to optimize at least one of latency, throughput, power, and performance, and executing the decoded instruction, by the execution circuit, to: atomically read a datum from a location identified by the destination identifier, perform an operation on the datum as specified by the opcode, the operation to use a source operand identified by the source identifier, and write a result back to the location.

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