公开(公告)号：US20240134432A1

公开(公告)日：2024-04-25

申请号：US18537697

申请日：2023-12-12

Applicant: Intel Corporation

Inventor： Akhilesh S. THYAGATURU ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Jonathan KYLE ,  Marek PIOTROWSKI

IPC: G06F1/20 ,  G06F9/455

CPC classification number: G06F1/206 ,  G06F9/45558 ,  G06F2009/45591

Abstract: A method is claimed. The method includes receiving information associated with a software application's workflow. The method includes receiving information that describes a platform's current power consumption state and current thermal state. The method includes selecting platform components to support execution of the workflow. The method includes prior to execution of the workflow upon the selected platform components, estimating a thermal impact to the platform's current thermal state as a consequence of the workflow's execution upon the selected platform components. The method includes determining a change to be made to a thermal cooling system of the platform in response to the estimating and causing the change to be made to the thermal cooling system prior to execution of at least a portion of the workflow on the platform.

公开(公告)号：US20230023229A1

公开(公告)日：2023-01-26

申请号：US17952835

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Karthik KUMAR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY ,  Susanne M. BALLE ,  Andrzej KURIATA ,  Nagabhushan CHITLUR

IPC: G06F3/06

Abstract: In a server system, a host computing platform can have a processing unit separate from the host processor to detect and respond to failure of the host processor. The host computing platform includes a memory to store data for the host processor. The processing unit has an interface to the host processor and the memory and an interface to a network external to the host processor and has access to the memory. In response to detection of failure of the host processor, the processing unit migrates data from the memory to another memory or storage.

公开(公告)号：US20200278804A1

公开(公告)日：2020-09-03

申请号：US16846994

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Tushar Sudhakar GOHAD ,  Mark A. SCHMISSEUR ,  Thomas WILLHALM

IPC: G06F3/06 ,  G06N3/063

Abstract: A memory request manager in a memory system registers a tenant for access to a plurality of memory devices, registers one or more service level agreement (SLA) requirements for the tenant for access to the plurality of memory devices, monitors usage of the plurality of memory devices by tenants, receives a memory request from the tenant to access a selected one of the plurality of memory devices, and allows the access when usage of the plurality of memory devices meets the one or more SLA requirements for the tenant.

公开(公告)号：US20200228630A1

公开(公告)日：2020-07-16

申请号：US16833448

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Dimitrios ZIAKAS ,  Mark A. SCHMISSEUR ,  Ned SMITH

IPC: H04L29/08 ,  H04L12/911 ,  H04L12/66

Abstract: A persistence service for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow an endpoint, such as an IoT device or client device, to specify criteria for achieving persistence for data stored in an edge resource. The persistence interface extends the storage and memory controllers to store data in accordance with the criteria, including determining whether a local or remote edge resource is best able to store data persistently in a manner that satisfies the criteria. The criteria include a persistence service level agreement, including a required time to persistence, cost of persistence and reliability level of persistence. Only edge resources that contain media, including storage subsystems and/or memory, capable of storing data persistently while satisfying the criteria will be permitted to service the request. The persistence service can include a discovery service to efficiently locate objects previously stored using the persistence service.

公开(公告)号：US20190121564A1

公开(公告)日：2019-04-25

申请号：US16221832

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Mustafa HAJEER ,  Thomas Willhalm ,  Amin FIROOZSHAHIAN ,  Chandan EGBERT

IPC: G06F3/06

Abstract: Examples relate to an approximative memory deduplication method, a controller apparatus or controller device for a memory or storage controller, a memory or storage controller, a computer system and to a computer program. The approximative memory deduplication method comprises determining a hash value of a data block. The hash value is based on a user-defined approximative hashing function. The approximative memory deduplication method comprises storing a quantized version of the data block based on the hash value using a memory or storage device of the computer system.

公开(公告)号：US20180278493A1

公开(公告)日：2018-09-27

申请号：US15470664

申请日：2017-03-27

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Thomas WILLHALM ,  Andrew HERDRICH ,  Edwin VERPLANKE

IPC: H04L12/24 ,  H04L12/947 ,  H04L5/00 ,  H04L12/911

CPC classification number: H04L41/5019 ,  H04L5/0055 ,  H04L41/0896 ,  H04L41/5003 ,  H04L47/783 ,  H04L49/25

Abstract: Examples include techniques to meet quality of service (QoS) requirements for a fabric point to point connection. Examples include an application hosted by a compute node coupled with a fabric requesting bandwidth for a point to point connection through the fabric and the request being granted or not granted based at least partially on whether bandwidth is available for allocation to meet one or more QoS requirements.

公开(公告)号：US20240103861A1

公开(公告)日：2024-03-28

申请号：US18533487

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Akhilesh S. THYAGATURU ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Mohit Kumar GARG

IPC: G06F9/30

CPC classification number: G06F9/3004

Abstract: An apparatus is described. The apparatus includes a memory module. The memory module includes a memory. The memory module includes function execution circuitry. The function execution circuitry is configurable to execute a producer function and a consumer function of a multi-function process. The memory module includes an interface to be coupled to a memory controller.

公开(公告)号：US20240013181A1

公开(公告)日：2024-01-11

申请号：US18474278

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Marcos CARRANZA ,  Mallikarjuna CHILAKALA ,  Francesc GUIM BERNAT ,  Karthik KUMAR

IPC: G06Q20/14 ,  G06Q20/38 ,  G06Q50/06

CPC classification number: G06Q20/145 ,  G06Q20/38215 ,  G06Q50/06

Abstract: Various examples relate to apparatuses, devices, methods and computer programs for a group leader and a group member of a group of nodes of a blockchain network. The apparatus for the group leader comprises interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to manage a membership of nodes of the blockchain network in the group of nodes, perform or delegate blockchain-related computational activity on behalf of the group of nodes according to an energy criterion.

公开(公告)号：US20230421374A1

公开(公告)日：2023-12-28

申请号：US17809297

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Kshitij A. DOSHI ,  Rita H. WOUHAYBI ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Marcos CARRANZA ,  Cesar MARTINEZ SPESSOT

IPC: H04L9/30 ,  H04L9/32

CPC classification number: H04L9/30 ,  H04L9/3247

Abstract: Examples relate to a computer system, a telemetry hub apparatus, a telemetry hub device, a telemetry hub method, a microservice apparatus, a microservice device, a microservice method and to corresponding computer programs. The telemetry apparatus is configured to obtain telemetry information from a plurality of microservices, and to provide access to the telemetry information for the plurality of microservices according to an access scheme.

公开(公告)号：US20230393956A1

公开(公告)日：2023-12-07

申请号：US18230387

申请日：2023-08-04

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Eoin WALSH ,  Karthik KUMAR ,  Marcos E. CARRANZA

IPC: G06F11/20

CPC classification number: G06F11/2002

Abstract: Examples described herein relate to failover of processes from a first network interface device to a second network interface device. A first programmable network interface device includes a network interface, a direct memory access (DMA) circuitry, a host interface, and at least one processor to execute a first process. A second programmable network interface device includes a network interface, a DMA circuitry, a host interface, and at least one processor. The at least one processor of the second programmable network interface device is to perform failover execution of the first process.