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公开(公告)号：US20240028544A1
公开(公告)日：2024-01-25
申请号：US18478003
申请日：2023-09-29
Applicant: Intel Corporation
Inventor： Sharath Raghava , Dheeraj Subbareddy , Kavitha Prasad , Ankireddy Nalamalpu , Harsha Gupta
CPC classification number: G06F13/4027 , G06F13/4282
Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.
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公开(公告)号：US11789883B2
公开(公告)日：2023-10-17
申请号：US16103709
申请日：2018-08-14
Applicant: Intel Corporation
Inventor： Sharath Raghava , Dheeraj Subbareddy , Kavitha Prasad , Ankireddy Nalamalpu , Harsha Gupta
CPC classification number: G06F13/4027 , G06F13/4282
Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.
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公开(公告)号：US11700002B2
公开(公告)日：2023-07-11
申请号：US17556917
申请日：2021-12-20
Applicant: Intel Corporation
Inventor： Sharath Raghava , Ankireddy Nalamalpu , Dheeraj Subbareddy , Harsha Gupta , James Ball , Kavitha Prasad , Sean R. Atsatt
IPC: H04L12/28 , H03K19/17736 , H03K19/17796 , H04L41/5019 , H04L41/5003
CPC classification number: H03K19/17736 , H03K19/17796 , H04L41/5019 , H04L41/5003
Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
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公开(公告)号：US20190050361A1
公开(公告)日：2019-02-14
申请号：US16103709
申请日：2018-08-14
Applicant: Intel Corporation
Inventor： Sharath Raghava , Dheeraj Subbareddy , Kavitha Prasad , Ankireddy Nalamalpu , Harsha Gupta
Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.
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