公开(公告)号：US20200151847A1

公开(公告)日：2020-05-14

申请号：US16190093

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： Travis SCHLUESSLER ,  Zack S. WATERS ,  Michael APODACA

IPC: G06T1/20 ,  G06T15/50 ,  G06T15/00 ,  G06F9/38 ,  G06T17/10

Abstract: Examples are described here that can be used to allocate primitive visibility determination to a particular graphics processor or group of graphics processors. The particular graphics processor or group of graphics processors can determine which region of a frame a primitive is visible in. For example, a frame can include multiple regions. One or more graphics processors can be assigned to a particular region to handle rasterization of primitives that are visible within the particular region. The one or more graphics processors assigned to a particular region can be free to perform other tasks and perform rasterization and additional tasks solely for the visible primitives.

公开(公告)号：US20180308210A1

公开(公告)日：2018-10-25

申请号：US16024750

申请日：2018-06-30

Applicant: INTEL CORPORATION

Inventor： Michael APODACA

IPC: G06T1/20 ,  G06F1/32 ,  G06F15/76

CPC classification number: G06T1/20 ,  G06F1/3212 ,  G06F1/3265 ,  G06F1/329 ,  G06F15/76 ,  G06T2200/28 ,  Y02D10/153 ,  Y02D10/174 ,  Y02D10/24 ,  Y02D10/28 ,  Y02D10/40

Abstract: Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.

公开(公告)号：US20220343554A1

公开(公告)日：2022-10-27

申请号：US17740754

申请日：2022-05-10

Applicant: INTEL CORPORATION

Inventor： Carson BROWNLEE ,  Carsten BENTHIN ,  Joshua BARCZAK ,  Kai XIAO ,  Michael APODACA ,  Prasoonkumar SURTI ,  Thomas RAOUX

IPC: G06T9/40 ,  G06T15/06 ,  G06T15/20 ,  G06T1/60

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

公开(公告)号：US20210082154A1

公开(公告)日：2021-03-18

申请号：US17003040

申请日：2020-08-26

Applicant: INTEL CORPORATION

Inventor： Carson BROWNLEE ,  Carsten BENTHIN ,  Joshua BARCZAK ,  Kai XIAO ,  Michael APODACA ,  Prasoonkumar SURTI ,  Thomas RAOUX

IPC: G06T9/40 ,  G06T15/06 ,  G06T15/20 ,  G06T1/60

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

公开(公告)号：US20210042987A1

公开(公告)日：2021-02-11

申请号：US17079191

申请日：2020-10-23

Applicant: INTEL CORPORATION

Inventor： Karthik VAIDYANATHAN ,  Michael APODACA ,  Thomas RAOUX ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Joshua BARCZAK

IPC: G06T15/06 ,  G06T1/60 ,  G06T9/00 ,  G06T5/00

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US20180144436A1

公开(公告)日：2018-05-24

申请号：US15688837

申请日：2017-08-28

Applicant: INTEL CORPORATION

Inventor： Michael APODACA

IPC: G06T1/20 ,  G06F1/32 ,  G06F15/76

CPC classification number: G06T1/20 ,  G06F1/3212 ,  G06F1/3265 ,  G06F1/329 ,  G06F15/76 ,  G06T2200/28 ,  Y02D10/153 ,  Y02D10/174 ,  Y02D10/24 ,  Y02D10/28 ,  Y02D10/40

Abstract: Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.