公开(公告)号：US20250093413A1

公开(公告)日：2025-03-20

申请号：US18963838

申请日：2024-11-29

Applicant: Intel Corporation

Inventor： Zhen ZHOU ,  Renzhi LIU ,  Jong-Ru GUO ,  Kenneth P. FOUST ,  Jason A. MIX ,  Kai XIAO ,  Zuoguo WU ,  Daqiao DU

IPC: G01R31/302 ,  G01R31/28 ,  G01R31/303 ,  H01P3/08 ,  H01Q9/16 ,  H04B5/48

Abstract: A high volume manufacturing (HVM) test system including a test device defining an opening configured to receive a package under test, the test device including an external access agent (EAA) including: a first leaky surface wave launcher for near field wireless communication, the first leaky surface wave launcher configured to wirelessly provide sideband signals to and wirelessly receive the sideband signals from a silicon package agent physically positioned in a separate package as the EAA; and a first transceiver electrically coupled to the first leaky surface wave launcher, the first transceiver configured to: process the sideband signals received by the first leaky surface wave launcher; and generate the sideband signals for wireless transmission by the first leaky surface wave launcher.

公开(公告)号：US20200211265A1

公开(公告)日：2020-07-02

申请号：US16236218

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Carson BROWNLEE ,  Joshua BARCZAK ,  Kai XIAO ,  Michael APODACA ,  Philip LAWS ,  Thomas RAOUX ,  Travis SCHLUESSLER

IPC: G06T15/06 ,  G06T15/00

Abstract: Cloud-based real time rendering. For example, one embodiment of a system comprises: a first graphics processing node to perform a first set of graphics processing operations to render a graphics scene, the first set of graphics processing operations comprising ray-tracing independent operations; an interconnect or network interface coupling the first graphics processing node to a second graphics processing node; the second graphics processing node to receive an indication of a current view of a user of the first graphics processing node and to receive or construct a view-independent surface generated by view-independent ray traversal and intersection operations; the second graphics processing node to responsively perform a view-dependent translation of the view-independent surface based on the current view of the user to generate a view-dependent surface and to provide the view-dependent surface to the first graphics processing node; and the first graphics processing node to perform a second set of graphics processing operations to complete rendering of the graphics scene using the view-dependent surface.

公开(公告)号：US20200083155A1

公开(公告)日：2020-03-12

申请号：US16128284

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Raul ENRIQUEZ SHIBAYAMA ,  Vijaya BODDU ,  Luis Nathan PEREZ ACOSTA ,  Francisco Javier GALARZA MEDINA ,  Kai XIAO ,  Luis ROSALES-GALVAN ,  Beom-Taek LEE ,  Carlos Alberto LIZALDE MORENO ,  Gaudencio HERNANDEZ SOSA ,  Mo LIU

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11

Abstract: Apparatuses, systems and methods associated with electrical routing layout of printed circuit boards and integrated circuit substrates are disclosed herein. In embodiments, an apparatus includes a first electrically conductive path that extends through a region, wherein the first electrically conductive path includes a first pad located at a surface of the region, a first via that extends through the region, and a first trace that extends in a first direction. The apparatus further includes a second electrically conductive path that extends through the region, wherein the second electrically conductive path includes a second pad located at the surface and adjacent to the first pad, a second via that extends through the region, and a second trace that extends in a second direction. Other embodiments may be described and/or claimed.

公开(公告)号：US20250118933A1

公开(公告)日：2025-04-10

申请号：US18989657

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Kai XIAO ,  Diego Mauricio CORTES HERNANDEZ ,  Luz Karine SANDOVAL GRANADOS ,  Jingbo LI ,  Raul ALCALA ARREOLA ,  Quresh BOHRA ,  Jose Manuel CANTOR GONZALEZ ,  Fabio RUIZ MOLINA ,  Carlos Guillermo TERRIQUEZ ARIAS ,  Adriana LOPEZ INIGUEZ

IPC: H01R13/6471 ,  H01R12/70 ,  H01R12/71 ,  H01R12/75 ,  H01R13/04

Abstract: Examples include techniques to improve signal integrity performance for a 3-connector design. The techniques include mounting a socket connector to a first side of a hot swap backplane such that pins of the first socket connector mirror pins of a second socket connector mounted to a second side of the hot swap backplane. The mirrored pins associated with routing data signals. The socket connector having a housing configured to receive a first plug connector of a cable assembly that has a second plug connector coupled with a processor baseboard socket connector.

公开(公告)号：US20230162428A1

公开(公告)日：2023-05-25

申请号：US17982766

申请日：2022-11-08

Applicant: INTEL CORPORATION

Inventor： Michael APODACA ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Timothy ROWLEY ,  Joshua BARCZAK ,  Travis SCHLUESSLER

IPC: G06T15/06 ,  G06F16/901 ,  G06F7/14 ,  G06F9/38

CPC classification number: G06T15/06 ,  G06F16/9027 ,  G06F7/14 ,  G06F9/3877 ,  G06N3/02

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US20210035349A1

公开(公告)日：2021-02-04

申请号：US16996208

申请日：2020-08-18

Applicant: INTEL CORPORATION

Inventor： Karthik VAIDYANATHAN ,  Michael APODACA ,  Thomas RAOUX ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Joshua BARCZAK

IPC: G06T15/06 ,  G06T1/60

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US20160134036A1

公开(公告)日：2016-05-12

申请号：US14539597

申请日：2014-11-12

Applicant: Intel Corporation

Inventor： Shaowu HUANG ,  Ifiok J. UMOH ,  Kai XIAO ,  Beom-Taek LEE

IPC: H01R12/70

CPC classification number: G06F13/4086

Abstract: A channel (e.g., memory channel) coupling a processor to multiple devices (e.g., DIMMs) is described. The channel has an interconnect topology with multiple interconnect portions coupled together with two or more junctions. At least one of these junctions has first and second interconnect portions that cross each other to form a plus-shaped junction. Also, the interconnect routing between the two or more junctions has an impedance matched to impedance of the two or more junctions.

Abstract translation: 描述了将处理器耦合到多个设备（例如，DIMM）的通道（例如，存储器通道）。 该通道具有互连拓扑，其中多个互连部分与两个或更多个结连接在一起。 这些结中的至少一个具有相互交叉以形成正形结的第一和第二互连部分。 而且，两个或多个结之间的互连布线具有与两个或多个结的阻抗匹配的阻抗。

公开(公告)号：US20240237193A1

公开(公告)日：2024-07-11

申请号：US18618075

申请日：2024-03-27

Applicant: Intel Corporation

Inventor： Yi HUANG ,  Xiaoning YE ,  Kai XIAO ,  James A. McCALL ,  Yanjie ZHU

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0253 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/10189

Abstract: An apparatus is described. The apparatus includes a memory module. The memory module includes a first printed circuit board having a first transmission line. The first printed circuit board has memory chips disposed thereon. The memory module includes a second printed board having a second transmission line that is coupled to the first transmission line to form a signal path through the first and second printed circuit boards. The second printed circuit board has greater flexibility than the first printed circuit board. The memory module includes a connector to align an I/O that is coupled to the second transmission line with a corresponding I/O that is associated with a motherboard that is to send and/or receive a signal to and/or from the signal path.

公开(公告)号：US20220343554A1

公开(公告)日：2022-10-27

申请号：US17740754

申请日：2022-05-10

Applicant: INTEL CORPORATION

Inventor： Carson BROWNLEE ,  Carsten BENTHIN ,  Joshua BARCZAK ,  Kai XIAO ,  Michael APODACA ,  Prasoonkumar SURTI ,  Thomas RAOUX

IPC: G06T9/40 ,  G06T15/06 ,  G06T15/20 ,  G06T1/60

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

公开(公告)号：US20220206064A1

公开(公告)日：2022-06-30

申请号：US17133659

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Zhen ZHOU ,  Renzhi LIU ,  Jong-Ru GUO ,  Kenneth P. FOUST ,  Jason A. MIX ,  Kai XIAO ,  Zuoguo WU ,  Daqiao DU

IPC: G01R31/302 ,  H01P3/08 ,  H01Q9/16 ,  H04B5/02 ,  G01R31/28 ,  G01R31/303

Abstract: A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.