公开(公告)号：US20220121447A1

公开(公告)日：2022-04-21

申请号：US17560363

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Abhishek Basak ,  Santosh Ghosh ,  Michael D. LeMay ,  David M. Durham

IPC: G06F9/38 ,  G06F9/30

Abstract: In one embodiment, a processor includes a memory hierarchy and a core. The core includes circuitry to access an encoded code pointer for a load instruction and perform a memory disambiguation (MD) lookup using a subset of address bits indicated by the encoded code pointer and context information indicated by one or more of the encoded code pointer or an encoded data pointer of the load instruction. The circuitry is further to determine, based on the MD lookup, that the load instruction is predicted to be independent from previous store instructions and forward the load instruction for out-of-order execution based on the determination.

公开(公告)号：US20210149825A1

公开(公告)日：2021-05-20

申请号：US17134406

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： David M. Durham ,  Karanvir S. Grewal ,  Michael D. LeMay ,  Salmin Sultana ,  Andrew James Weiler

IPC: G06F12/14 ,  G06F9/50 ,  G06F9/30

Abstract: A processor includes a register to store an encoded pointer to a variable in stack memory. The encoded pointer includes an encrypted portion and a fixed plaintext portion of a memory address corresponding to the variable. The processor further includes circuitry to, in response to a memory access request for associated with the variable, decrypt the encrypted portion of the encoded pointer to obtain first upper address bits of the memory address and a memory allocation size for a variable, decode the encoded pointer to obtain the memory address, verify the memory address is valid based, at least in part on the memory allocation size, and in response to determining that the memory address is valid, allow the memory access request.

公开(公告)号：US12032486B2

公开(公告)日：2024-07-09

申请号：US17560360

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Abhishek Basak ,  Santosh Ghosh ,  Michael D. LeMay ,  David M. Durham

IPC: G06F12/1027 ,  G06F9/38

CPC classification number: G06F12/1027 ,  G06F9/3818 ,  G06F2212/68

Abstract: In one embodiment, a processor includes circuitry to decode an instruction referencing an encoded data pointer that includes a set of plaintext linear address bits and a set of encrypted linear address bits. The processor also includes circuitry to perform a speculative lookup in a translation lookaside buffer (TLB) using the plaintext linear address bits to obtain physical address, buffer a set of architectural predictor state values based on the speculative TLB lookup, and speculatively execute the instruction using the physical address obtained from the speculative TLB lookup. The processor also includes circuitry to determine whether the speculative TLB lookup was correct and update a set of architectural predictor state values of the core using the buffered architectural predictor state values based on a determination that the speculative TLB lookup was correct.

公开(公告)号：US11711201B2

公开(公告)日：2023-07-25

申请号：US17213568

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Andrew James Weiler ,  David M. Durham ,  Michael D. LeMay ,  Sergej Deutsch ,  Michael E. Kounavis ,  Salmin Sultana ,  Karanvir S. Grewal

IPC: H04L9/06 ,  G06F9/50 ,  G06F12/14 ,  H04L9/08 ,  H04L9/32 ,  G06F12/121

CPC classification number: H04L9/0618 ,  G06F9/5016 ,  G06F12/121 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1458 ,  G06F2212/7207

Abstract: In one embodiment, an encoded pointer is constructed from a stack pointer that includes offset. The encoded pointer includes the offset value and ciphertext that is based on encrypting a portion of a decorated pointer that includes a maximum offset value. Stack data is encrypted based on the encoded pointer, and the encoded pointer is stored in a stack pointer register of a processor. To access memory, a decoded pointer is constructed based on decrypting the ciphertext of the encoded pointer and the offset value. Encrypted stack data is accessed based on the decoded pointer, and the encrypted stack is decrypted based on the encoded pointer.

公开(公告)号：US20220138329A1

公开(公告)日：2022-05-05

申请号：US17576533

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Michael D. LeMay ,  David M. Durham ,  Stanislav Shwartsman

IPC: G06F21/60 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/48 ,  G06F21/72 ,  H04L9/06 ,  G06F12/06 ,  G06F12/0875 ,  G06F21/79 ,  G06F9/455 ,  G06F12/0811 ,  G06F21/12 ,  H04L9/08 ,  G06F12/14 ,  G06F9/32 ,  G06F9/50 ,  G06F12/02 ,  H04L9/14 ,  G06F21/62

Abstract: In one embodiment, a processor of a cryptographic computing system includes a register to store an encryption key and address generation circuitry to obtain a pointer representing a linear address to be accessed by a read or write operation, the pointer being at least partially encrypted, obtain the key from the register and a context value, decrypt the encrypted portion of the pointer using the key and the context value as a tweak input, and generate an effective address for use in the read or write operation based on an output of the decryption.

公开(公告)号：US20220121578A1

公开(公告)日：2022-04-21

申请号：US17560360

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Abhishek Basak ,  Santosh Ghosh ,  Michael D. LeMay ,  David M. Durham

IPC: G06F12/1027 ,  G06F9/38

Abstract: In one embodiment, a processor includes circuitry to decode an instruction referencing an encoded data pointer that includes a set of plaintext linear address bits and a set of encrypted linear address bits. The processor also includes circuitry to perform a speculative lookup in a translation lookaside buffer (TLB) using the plaintext linear address bits to obtain physical address, buffer a set of architectural predictor state values based on the speculative TLB lookup, and speculatively execute the instruction using the physical address obtained from the speculative TLB lookup. The processor also includes circuitry to determine whether the speculative TLB lookup was correct and update a set of architectural predictor state values of the core using the buffered architectural predictor state values based on a determination that the speculative TLB lookup was correct.

公开(公告)号：US20220100907A1

公开(公告)日：2022-03-31

申请号：US17547875

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Abhishek Basak ,  Salmin Sultana ,  Santosh Ghosh ,  Michael D. LeMay ,  Karanvir S. Grewal ,  David M. Durham

IPC: G06F21/72 ,  G06F9/30 ,  G06F9/38

Abstract: In one embodiment, a processor includes a memory hierarchy that stores encrypted data, tracking circuitry that tracks an execution context for instructions executed by the processor, and cryptographic computing circuitry to encrypt/decrypt data that is stored in the memory hierarchy. The cryptographic computing circuitry obtains context information from the tracking circuitry for a load instruction to be executed by the processor, where the context information indicates information about branch predictions made by a branch prediction unit of the processor, and decrypts the encrypted data using a key and the context information as a tweak input to the decryption.

公开(公告)号：US20210240638A1

公开(公告)日：2021-08-05

申请号：US17214222

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  David M. Durham ,  Karanvir S. Grewal ,  Michael D. LeMay ,  Michael E. Kounavis

IPC: G06F12/14 ,  G06F12/121 ,  G06F9/50

Abstract: Technologies disclosed herein provide one example of a processor that includes a register to store a first encoded pointer for a first memory allocation for an application and circuitry coupled to memory. Size metadata is stored in first bits of the first encoded pointer and first memory address data associated with the first memory allocation is stored in second bits of the first encoded pointer. The circuitry is configured to determine a first memory address of a first marker region in the first memory allocation, obtain current data from the first marker region at the first memory address, compare the current data to a reference marker stored separately from the first memory allocation, and determine that the first memory allocation is in a first state in response to a determination that the current data corresponds to the reference marker.

公开(公告)号：US20210218547A1

公开(公告)日：2021-07-15

申请号：US17213568

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Andrew James Weiler ,  David M. Durham ,  Michael D. LeMay ,  Sergej Deutsch ,  Michael E. Kounavis ,  Salmin Sultana ,  Karanvir S. Grewal

IPC: H04L9/06

Abstract: In one embodiment, an encoded pointer is constructed from a stack pointer that includes offset. The encoded pointer includes the offset value and ciphertext that is based on encrypting a portion of a decorated pointer that includes a maximum offset value. Stack data is encrypted based on the encoded pointer, and the encoded pointer is stored in a stack pointer register of a processor. To access memory, a decoded pointer is constructed based on decrypting the ciphertext of the encoded pointer and the offset value. Encrypted stack data is accessed based on the decoded pointer, and the encrypted stack is decrypted based on the encoded pointer.