公开(公告)号：US20250006666A1

公开(公告)日：2025-01-02

申请号：US18215480

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo

IPC: H01L23/66 ,  H01P3/08 ,  H01P11/00

Abstract: An integrated circuit (IC) device includes an IC die on a substrate, and the substrate includes a group of conductive lines between a high-permittivity dielectric layer and a low-permittivity dielectric layer, with a ground plane separated from the conductive lines by either the high- or low-permittivity dielectric layer. The substrate may include other low-permittivity dielectric layers. The substrate may include other groups of conductive lines between ground planes. The high-permittivity dielectric layer may be within a low-permittivity dielectric core layer.

公开(公告)号：US20250006588A1

公开(公告)日：2025-01-02

申请号：US18216830

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo

IPC: H01L23/427 ,  H01L21/48 ,  H01L25/18

Abstract: A semiconductor assembly may include a package substrate. A semiconductor assembly may include a first semiconductor die on the package substrate. A semiconductor assembly may include a first heat spreader heat spreader is attached to the first semiconductor die opposite the package substrate, the heat spreader comprising a mesh infused with phase change material, wherein the heat spreader is configured to dissipate heat from the first semiconductor die.

公开(公告)号：US20230178502A1

公开(公告)日：2023-06-08

申请号：US17542107

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Poh Boon Khoo

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L25/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2224/05017 ,  H01L2225/06589 ,  H01L2225/0651

Abstract: Methods and apparatus to reduce thickness of on-package memory architectures are disclosed. An on-package memory architecture includes a memory die; a bonding pad including a first surface and a second surface opposite the first surface; a wire bond electrically coupling the memory die to the first surface of the bonding pad; and a metal stub protruding from the second surface of the bonding pad. The metal stub is to electrically couple with a contact pad on a package substrate of an integrated circuit (IC) package.

公开(公告)号：US11322434B2

公开(公告)日：2022-05-03

申请号：US16912595

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh

IPC: H01R9/00 ,  H01L23/498 ,  H05K3/34 ,  H01L21/48

Abstract: Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate.

公开(公告)号：US20220077047A1

公开(公告)日：2022-03-10

申请号：US17529093

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

IPC: H01L23/498 ,  H01L23/552 ,  H01L21/48

Abstract: A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.

公开(公告)号：US10998262B2

公开(公告)日：2021-05-04

申请号：US16384348

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh ,  Amruthavalli Pallavi Alur ,  Debendra Mallik

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.