公开(公告)号：US20210294641A1

公开(公告)日：2021-09-23

申请号：US17342476

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  William A. Braun ,  Rajshree A. Chabukswar ,  Leigh Davies ,  Russell J. Fenger ,  Alexander Gendler ,  Raoul V. Rivas Toledano ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F11/30 ,  G06F11/34

Abstract: Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.

公开(公告)号：US10656697B2

公开(公告)日：2020-05-19

申请号：US15911577

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/34 ,  G06F11/30 ,  G06F1/3206

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US10592244B2

公开(公告)日：2020-03-17

申请号：US15423143

申请日：2017-02-02

Applicant: INTEL CORPORATION

Inventor： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC: G06F9/30

Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.

公开(公告)号：US20190050041A1

公开(公告)日：2019-02-14

申请号：US15911577

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/34 ,  G06F11/30

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.