公开(公告)号：US20200210178A1

公开(公告)日：2020-07-02

申请号：US16811242

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC: G06F9/30

Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.

公开(公告)号：US09910475B2

公开(公告)日：2018-03-06

申请号：US14580553

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F1/3206 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/348 ,  G06F2201/86

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US10445204B2

公开(公告)日：2019-10-15

申请号：US14865715

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Richard B. O'Connor ,  Beeman C. Strong ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar

IPC: G06F9/38 ,  G06F11/30

Abstract: A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.

公开(公告)号：US20250004851A1

公开(公告)日：2025-01-02

申请号：US18344092

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Yevgeni Sabin ,  Madhusudan Chidambaram ,  Refael Mizrahi ,  Efraim Rotem ,  Rajshree A. Chabukswar ,  Eliezer Weissmann ,  Stephen H. Gunther ,  Hisham Abu-Salah ,  Sneha Gohad ,  Anusha Ramachandran ,  Praveen Koduru ,  Hadas Beja ,  Nofar Mani ,  Hadar Ringel ,  Avishai Wagner

IPC: G06F9/50 ,  G06F9/54

Abstract: In one embodiment, a processor includes: at least one first core to execute instructions; at least one second core to execute instructions; and a control circuit coupled to the at least one first core and the at least one second core. The control circuit may be configured to: receive workload telemetry information regarding a workload for execution on the processor; determine a QoS distribution based at least in part on the workload telemetry information; receive a predicted workload type, the predicted workload type based at least in part on the QoS distribution; and cause at least one of the at least one first core or the at least one second core to be parked based on the predicted workload type and the QoS distribution. Other embodiments are described and claimed.

公开(公告)号：US12008398B2

公开(公告)日：2024-06-11

申请号：US16729370

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Julius Mandelblat ,  Eliezer Weissmann ,  Rajshree A. Chabukswar ,  Michael W. Chynoweth

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/32 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/30101 ,  G06F9/321 ,  G06F9/485

Abstract: Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

公开(公告)号：US20230092268A1

公开(公告)日：2023-03-23

申请号：US17992407

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC: G06F9/30

Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.

公开(公告)号：US20230091167A1

公开(公告)日：2023-03-23

申请号：US17482944

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Vijay C. Bahirji

IPC: G06F9/38 ,  G06F9/30

Abstract: An embodiment of an integrated circuit may comprise an instruction decoder to decode one or more instructions to be executed by a core, and circuitry coupled to the instruction decoder, the circuitry to determine if a decoded instruction involves a page to be fetched, and determine one or more hints for one or more optional pages that may be fetched along with the page for the decoded instruction. Other embodiments are disclosed and claimed.

公开(公告)号：US20210200580A1

公开(公告)日：2021-07-01

申请号：US16729370

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Julius Mandelblat ,  Eliezer Weissmann ,  Rajshree A. Chabukswar ,  Michael W. Chynoweth

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/32

Abstract: Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.

公开(公告)号：US20180217839A1

公开(公告)日：2018-08-02

申请号：US15423143

申请日：2017-02-02

Applicant: INTEL CORPORATION

Inventor： Michael W. Chynoweth ,  Jonathan D. Combs ,  Joseph K. Olivas ,  Beeman C. Strong ,  Rajshree A. Chabukswar ,  Ahmad Yasin ,  Jason W. Brandt ,  Ofer Levy ,  John M. Esper ,  Andreas Kleen ,  Christopher M. Chrulski

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3005

Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.

公开(公告)号：US20240103914A1

公开(公告)日：2024-03-28

申请号：US17954411

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Russell J. Fenger ,  Rajshree A. Chabukswar ,  Benjamin Graniello ,  Monica Gupta ,  Guy M. Therien ,  Michael W. Chynoweth

IPC: G06F9/48 ,  G06F1/3228

CPC classification number: G06F9/4887 ,  G06F1/3228

Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions; at least one monitor coupled to the plurality of cores to measure at least one of power information, temperature information, or scalability information; and a control circuit coupled to the at least one monitor. Based at least in part on the at least one of the power information, the temperature information, or the scalability information, the control circuit is to notify an operating system that one or more of the plurality of cores are to transition to a forced idle state in which non-affinitized workloads are prevented from being scheduled. Other embodiments are described and claimed.