公开(公告)号：US10467012B2

公开(公告)日：2019-11-05

申请号：US15394458

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Yoav Zach ,  Boris Ginzburg ,  Ronny Ronen

IPC: G06F9/38 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/1072 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1045 ,  G06F3/06 ,  G06F12/02 ,  G06F12/14

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US09747221B2

公开(公告)日：2017-08-29

申请号：US14862745

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Gad Sheaffer ,  Boris Ginzburg ,  Ronny Ronen ,  Eliezer Weissmann

IPC: G06F12/1027 ,  G06F12/126 ,  G06F13/16 ,  G06F12/0804

CPC classification number: G06F12/1027 ,  G06F12/0804 ,  G06F12/126 ,  G06F13/1663 ,  G06F2212/303 ,  G06F2212/657 ,  G06F2212/684

Abstract: A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing unit (GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. The device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.