公开(公告)号：US09971688B2

公开(公告)日：2018-05-15

申请号：US15394539

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Yoav Zach ,  Boris Ginzburg ,  Ronny Ronen

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1009 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US10078519B2

公开(公告)日：2018-09-18

申请号：US15221557

申请日：2016-07-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Yoav Zach ,  Boris Ginzburg ,  Ronny Ronen

IPC: G06F12/10 ,  G06F9/38 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/1072 ,  G06F12/0875 ,  G06F12/1009

CPC classification number: G06F9/3851 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US10467012B2

公开(公告)日：2019-11-05

申请号：US15394458

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Yoav Zach ,  Boris Ginzburg ,  Ronny Ronen

IPC: G06F9/38 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/1072 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1045 ,  G06F3/06 ,  G06F12/02 ,  G06F12/14

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.