公开(公告)号：US11700002B2

公开(公告)日：2023-07-11

申请号：US17556917

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H04L12/28 ,  H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

CPC classification number: H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US20190050361A1

公开(公告)日：2019-02-14

申请号：US16103709

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

IPC: G06F13/40 ,  G06F13/42

Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.

公开(公告)号：US12237831B2

公开(公告)日：2025-02-25

申请号：US18198122

申请日：2023-05-16

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/177 ,  H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US12204441B2

公开(公告)日：2025-01-21

申请号：US17133799

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Nagabhushan Chitlur ,  Harsha Gupta

IPC: G06F12/02 ,  G06F1/30 ,  G06F9/30 ,  G06F12/0891 ,  G06F12/0895

Abstract: A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.

公开(公告)号：US11342918B2

公开(公告)日：2022-05-24

申请号：US17033524

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Harsha Gupta ,  James Ball ,  Kavitha Prasad ,  Sean R. Atsatt

IPC: H03K19/177 ,  H03K19/17736 ,  H03K19/17796 ,  H04L41/5019 ,  H04L41/5003

Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

公开(公告)号：US20210182187A1

公开(公告)日：2021-06-17

申请号：US17133799

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Sharath Raghava ,  Nagabhushan Chitlur ,  Harsha Gupta

IPC: G06F12/02 ,  G06F12/0891 ,  G06F12/0895 ,  G06F9/30 ,  G06F1/30

Abstract: A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.