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    Bitcoin mining hardware accelerator with optimized message digest and message scheduler datapath
    11.
    发明授权
    Bitcoin mining hardware accelerator with optimized message digest and message scheduler datapath 有权

    公开(公告)号：US10755242B2

    公开(公告)日：2020-08-25

    申请号：US15274200

    申请日：2016-09-23

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

    IPC: G06Q20/06 ,  G09C1/00 ,  G06Q20/02 ,  H04L9/06 ,  G06F9/48 ,  G06Q20/38

    Abstract: A Bitcoin mining hardware accelerator is described. A System on Chip implementing a Bitcoin mining hardware accelerator may include a processor core and a hardware accelerator coupled to the processor core, the hardware accelerator to mine digital currency. The hardware accelerator may include a first computational block, including a message digest datapath, wherein the first computational block is to: precompute a first summation of a 32-bit message (Wi), a 32-bit round constant (Ki), and a content of a first shifted state register (Gi−1), and store a result of the first summation in a state register (Hi). The Bitcoin mining hardware accelerator may further include a second computational block comprising a message scheduler datapath.

    SMS4 acceleration hardware
    13.
    发明授权
    SMS4 acceleration hardware 有权
    SMS4加速硬件

    公开(公告)号：US09503256B2

    公开(公告)日：2016-11-22

    申请号：US14582707

    申请日：2014-12-24

    Applicant: Intel Corporation

    Inventor： Kirk Yap ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

    IPC: H04L9/00 ,  H04L9/08 ,  H04L9/14

    CPC classification number: H04L9/0822 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

    Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

    Abstract translation: 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮密钥扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

    Unified AES-SMS4—Camellia symmetric key block cipher acceleration
    18.
    发明授权
    Unified AES-SMS4—Camellia symmetric key block cipher acceleration 有权

    公开(公告)号：US11121856B2

    公开(公告)日：2021-09-14

    申请号：US16010206

    申请日：2018-06-15

    Applicant: Intel Corporation

    Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

    IPC: H04L9/06 ,  G09C1/00 ,  G06F7/72

    Abstract: Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.

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