公开(公告)号：US09824037B2

公开(公告)日：2017-11-21

申请号：US14882824

申请日：2015-10-14

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US20150081999A1

公开(公告)日：2015-03-19

申请号：US14286055

申请日：2014-05-23

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F12/02

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

摘要翻译： 一般来说，本公开包括具有集成在处理器内的多个可编程单元的装置。 该装置具有将单个地址空间中的地址映射到多个可编程单元内的资源的电路，其中单个地址空间包括针对多个可编程单元中的不同可编程单元中的不同资源的地址，并且其中存在一对一 单个地址空间中的各个地址与多个可编程单元内的资源之间的对应关系。

公开(公告)号：US08732548B2

公开(公告)日：2014-05-20

申请号：US13793358

申请日：2013-03-11

申请人： Intel Corporation

发明人： Vinodh Gopal ,  Shay Gueron ,  Gilbert Wolrich ,  Wajdi Feghali ,  Kirk Yap ,  Bradley Burres

IPC分类号： H03M13/00

CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/091

摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.

摘要翻译： 提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。 灵活的CRC指令使用可编程的n位多项式来执行CRC操作。 通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

公开(公告)号：US20160071558A1

公开(公告)日：2016-03-10

申请号：US14882867

申请日：2015-10-14

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G11C7/10 ,  G06F15/173

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US20160070664A1

公开(公告)日：2016-03-10

申请号：US14882897

申请日：2015-10-14

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F13/20 ,  G06F13/40

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US20160034420A1

公开(公告)日：2016-02-04

申请号：US14882824

申请日：2015-10-14

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F15/76

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09830284B2

公开(公告)日：2017-11-28

申请号：US14809423

申请日：2015-07-27

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09047082B2

公开(公告)日：2015-06-02

申请号：US14254233

申请日：2014-04-16

申请人： Intel Corporation

发明人： Vinodh Gopal ,  Shay Gueron ,  Gilbert Wolrich ,  Wajdi Feghali ,  Kirk Yap ,  Bradley Burres

IPC分类号： G06F11/00 ,  G06F9/30 ,  H03M13/09 ,  G06F11/10

CPC分类号： G06F9/30145 ,  G06F9/30018 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/091

摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.

摘要翻译： 提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。 灵活的CRC指令使用可编程的n位多项式来执行CRC操作。 通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

公开(公告)号：US09503256B2

公开(公告)日：2016-11-22

申请号：US14582707

申请日：2014-12-24

申请人： Intel Corporation

发明人： Kirk Yap ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

IPC分类号： H04L9/00 ,  H04L9/08 ,  H04L9/14

CPC分类号： H04L9/0822 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

摘要： Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

摘要翻译： 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮密钥扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

公开(公告)号：US20160019178A1

公开(公告)日：2016-01-21

申请号：US14809423

申请日：2015-07-27

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F13/40 ,  G06F13/28 ,  G06F3/06

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.