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    Compression engine with configurable search depths and window sizes
    3.
    发明授权
    Compression engine with configurable search depths and window sizes 有权

    公开(公告)号：US12021550B2

    公开(公告)日：2024-06-25

    申请号：US17119892

    申请日：2020-12-11

    Applicant: Intel Corporation

    Inventor： Smita Kumar ,  Sailesh Bissessur ,  David K. Cassetti ,  Stephen T. Palermo

    IPC: G06F16/00 ,  G06F16/22 ,  H03M7/30 ,  H03M7/40

    CPC classification number: H03M7/3086 ,  G06F16/2255 ,  H03M7/40

    Abstract: Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.

    HARDWARE-BASED GENERATION OF UNCOMPRESSED DATA BLOCKS
    4.
    发明公开
    HARDWARE-BASED GENERATION OF UNCOMPRESSED DATA BLOCKS 审中-公开

    公开(公告)号：US20230342206A1

    公开(公告)日：2023-10-26

    申请号：US18214830

    申请日：2023-06-27

    Applicant: Intel Corporation

    Inventor： Laurent Coquerel ,  Fei Wang ,  Smita Kumar ,  Phani Krishna Sagiraju ,  John J. Browne

    IPC: G06F9/50 ,  H03M7/30

    CPC classification number: G06F9/5027 ,  H03M7/30

    Abstract: An accelerator or system including an accelerator can include an input interface to receive input data to be compressed and user application parameters for invocation of compression. The accelerator can include circuitry to identify a compression algorithm from configuration data provided with the input data. The user application parameters may not include parameters specifying entropy thresholds for compression of the input data. The circuitry can generate headers specific to the compression algorithm. The circuitry can generate uncompressed data blocks comprising blocks of the input data and corresponding headers. The circuitry can determine whether to provide the uncompressed data blocks or compressed data blocks based at least in part on entropy of the input data. Other methods, systems, and apparatuses are described.

    HARDWARE ACCELERATION OF DATA REDUCTION OPERATIONS
    6.
    发明公开
    HARDWARE ACCELERATION OF DATA REDUCTION OPERATIONS 审中-公开

    公开(公告)号：US20240128982A1

    公开(公告)日：2024-04-18

    申请号：US18397651

    申请日：2023-12-27

    Applicant: Intel Corporation

    Inventor： Smita Kumar ,  Patrick Fleming

    IPC: H03M7/30 ,  H03M7/32

    CPC classification number: H03M7/3068 ,  H03M7/3048

    Abstract: A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.

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