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    LOCKING AND POSITION STATUS DETECTION SCHEME FOR AN ELECTRONIC DEVICE
    11.
    发明申请
    LOCKING AND POSITION STATUS DETECTION SCHEME FOR AN ELECTRONIC DEVICE 有权

    公开(公告)号：US20210011520A1

    公开(公告)日：2021-01-14

    申请号：US17033561

    申请日：2020-09-25

    Applicant: Intel Corporation

    Inventor： Praveen Kashyap Ananta Bhat ,  Tarakesava Reddy Koki ,  Jaison Fernandez ,  Ruchi Sitaram Padekar

    IPC: G06F1/16

    Abstract: An example apparatus comprises a first member with a first surface, where the first member is movable relative to a second member with a second surface. The first member comprises a first magnet configured to produce a first magnetic field. The second member comprises a sensor operatively connected to a processor and a second magnet adjacent to the sensor. In a first position, the first magnet and the second magnet are engaged to magnetically hold the first member to the second member such that at least a portion of the first surface of the first member opposes at least a portion of the second surface of the second member. In the first position, the sensor is to detect the first magnetic field produced by the first magnet and is to send a signal to the processor in response to detecting the first magnetic field produced by the first magnet.

    REDUCTION OF SKEW BETWEEN POSITIVE AND NEGATIVE CONDUCTORS CARRYING A DIFFERENTIAL PAIR OF SIGNALS
    13.
    发明申请
    REDUCTION OF SKEW BETWEEN POSITIVE AND NEGATIVE CONDUCTORS CARRYING A DIFFERENTIAL PAIR OF SIGNALS 审中-公开

    公开(公告)号：US20190041458A1

    公开(公告)日：2019-02-07

    申请号：US15945169

    申请日：2018-04-04

    Applicant: Intel Corporation

    Inventor： Tarakesava Reddy Koki ,  Phani Kumar Alaparthi

    IPC: G01R31/317 ,  H03K5/01 ,  H05K1/02

    Abstract: A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.

    Power saving for type-C connectors
    16.
    发明授权
    Power saving for type-C connectors 有权

    公开(公告)号：US11474589B2

    公开(公告)日：2022-10-18

    申请号：US17407060

    申请日：2021-08-19

    Applicant: Intel Corporation

    Inventor： Tarakesava Reddy Koki ,  Phani K Alaparthi ,  Ranganadh Kss ,  Shobhit Chahar

    IPC: G06F1/3234 ,  H02J7/00 ,  H02J9/00

    Abstract: Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.

    POWER SAVING FOR TYPE-C CONNECTORS
    17.
    发明申请
    POWER SAVING FOR TYPE-C CONNECTORS 有权

    公开(公告)号：US20210382541A1

    公开(公告)日：2021-12-09

    申请号：US17407060

    申请日：2021-08-19

    Applicant: Intel Corporation

    Inventor： Tarakesava Reddy Koki ,  Phani K Alaparthi ,  Ranganadh KSS ,  Shobhit Chahar

    IPC: G06F1/3234 ,  H02J7/00 ,  H02J9/00

    Abstract: Described are mechanisms and methods to facilitate power saving in Type-C connectors. Some embodiments may comprise an interface to a Configuration Channel (CC) signal path and to a ground signal path of a Universal Serial Bus (USB) Type-C connector port, a first circuitry, and a second circuitry. The first circuitry may be operable to place toggled values on the CC signal path. The second circuitry may be operable to couple the ground signal path to a detection signal path. The placement of the toggled values on the CC signal path is enabled when the detection signal path carries a first value that corresponds with the USB Type-C connector port being connected to a USB Type-C device, and may be disabled when the detection signal path carries a second value that corresponds with the USB Type-C connector port not being connected to a USB Type-C device.

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