公开(公告)号：US20230369426A1

公开(公告)日：2023-11-16

申请号：US17742636

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Van H. Le ,  Timothy Jen ,  Kamal H. Baloch ,  Mark Armstrong ,  Albert B. Chen ,  Moshe Dolejsi ,  Shailesh Kumar Madisetti ,  Afrin Sultana ,  Deepyanti Taneja ,  Vishak Venkatraman

IPC: H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/41733 ,  H01L29/78618 ,  H01L29/7869 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/10805

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

公开(公告)号：US20230307291A1

公开(公告)日：2023-09-28

申请号：US17656366

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Moshe Dolejsi ,  Harish Ganapathy ,  Travis W. Lajoie ,  Deepyanti Taneja ,  Huiying Liu ,  Cheng Tan ,  Timothy Jen ,  Van H. Le ,  Abhishek A. Sharma

IPC: H01L21/768 ,  H01L27/108 ,  H01L23/522

CPC classification number: H01L21/76829 ,  H01L21/76859 ,  H01L23/5226 ,  H01L27/10852

Abstract: An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.