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公开(公告)号：US20200313084A1
公开(公告)日：2020-10-01
申请号：US16367136
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Michael Robinson , Huiying Liu
Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer. The magnetic junction further includes a pinning structure above the conductive layer, a fixed magnet above the pinning structure, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier layer and a second electrode above the free magnet. The conductive layer including iridium and the pinning structure including iridium provide switching efficiency.
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公开(公告)号：US20230369509A1
公开(公告)日：2023-11-16
申请号：US17742638
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： Jisoo Kim , Xiaoye Qin , Timothy Jen , Harish Ganapathy , Van H. Le , Huiying Liu , Prem Chanani , Cheng Tan , Shailesh Kumar Madisetti , Abhishek Anil Sharma , Brian Wadsworth , Vishak Venkatraman , Andre Baran
IPC: H01L29/786 , H01L23/528 , H01L27/108
CPC classification number: H01L29/7869 , H01L23/5283 , H01L27/10814
Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.
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公开(公告)号：US20230317615A1
公开(公告)日：2023-10-05
申请号：US17708051
申请日：2022-03-30
Applicant: Intel Corporation
Inventor： Deepyanti Taneja , Travis W. Lajoie , Abhishek Anil Sharma , Gregory J. George , Tarannum Tiasha , Huiying Liu , Yue Liu , Moshe Dolejsi , Vinaykumar V. Hadagali , Shardul Wadekar , Vladimir Nikitin , Albert B. Chen , Daniel J. Schinke , James O'Donnell
IPC: H01L23/532 , H01L27/12
CPC classification number: H01L23/53295 , H01L27/1248 , H01L27/1259 , H01L27/1255 , H01L23/5226
Abstract: An integrated circuit includes a first layer, and a second layer above the first layer. A third layer is between a first section of the first layer and a first section of the second layer. A fourth layer is laterally adjacent to the third layer, the fourth layer between a second section of the first layer and a second section of the second layer. In an example, a first dielectric material of the third layer is different (e.g., one or both of compositionally different and structurally different) from a second dielectric material of the fourth layer. In an example, the third and fourth layers are etch stop layers. In some cases, the third and fourth layers are coplanar with each other with respect to their top surfaces, or their bottom surfaces, or both their top and bottom surfaces.
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Patent Agency Ranking
公开(公告)号：US20230307291A1
公开(公告)日：2023-09-28
申请号：US17656366
申请日：2022-03-24
Applicant: Intel Corporation
Inventor： Moshe Dolejsi , Harish Ganapathy , Travis W. Lajoie , Deepyanti Taneja , Huiying Liu , Cheng Tan , Timothy Jen , Van H. Le , Abhishek A. Sharma
IPC: H01L21/768 , H01L27/108 , H01L23/522
CPC classification number: H01L21/76829 , H01L21/76859 , H01L23/5226 , H01L27/10852
Abstract: An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.
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公开(公告)号：US11737368B2
公开(公告)日：2023-08-22
申请号：US16367136
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Michael Robinson , Huiying Liu
Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer. The magnetic junction further includes a pinning structure above the conductive layer, a fixed magnet above the pinning structure, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier layer and a second electrode above the free magnet. The conductive layer including iridium and the pinning structure including iridium provide switching efficiency.
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公开(公告)号：US10897009B2
公开(公告)日：2021-01-19
申请号：US16414956
申请日：2019-05-17
Applicant: INTEL CORPORATION
Inventor： Niloy Mukherjee , Ravi Pillarisetty , Prashant Majhi , Uday Shah , Ryan E Arch , Markus Kuhn , Justin S. Brockman , Huiying Liu , Elijah V Karpov , Kaan Oguz , Brian S. Doyle , Robert S. Chau
IPC: H01L45/00
Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.
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公开(公告)号：US10943950B2
公开(公告)日：2021-03-09
申请号：US16367126
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Aaron Littlejohn , Michael Robinson , Huiying Liu
Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.
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8.发明申请公开(公告)号：US20200312907A1
公开(公告)日：2020-10-01
申请号：US16367126
申请日：2019-03-27
Applicant: Intel Corporation
Inventor： Daniel Ouellette , Christopher Wiegand , Justin Brockman , Tofizur Rahman , Oleg Golonzka , Angeline Smith , Andrew Smith , James Pellegren , Aaron Littlejohn , Michael Robinson , Huiying Liu
Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.
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