公开(公告)号：US20230369340A1

公开(公告)日：2023-11-16

申请号：US17742651

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Van H. Le ,  Timothy Jen ,  Vishak Venkatraman ,  Shailesh Kumar Madisetti ,  Cheng Tan ,  Harish Ganapathy ,  James Pellegren ,  Kamal H. Baloch ,  Abhishek Anil Sharma

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L27/1225 ,  H01L29/7869 ,  H01L23/5283 ,  H01L27/1255 ,  H01L27/10805

Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.

公开(公告)号：US20230369426A1

公开(公告)日：2023-11-16

申请号：US17742636

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Van H. Le ,  Timothy Jen ,  Kamal H. Baloch ,  Mark Armstrong ,  Albert B. Chen ,  Moshe Dolejsi ,  Shailesh Kumar Madisetti ,  Afrin Sultana ,  Deepyanti Taneja ,  Vishak Venkatraman

IPC: H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/41733 ,  H01L29/78618 ,  H01L29/7869 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/10805

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

公开(公告)号：US20230371233A1

公开(公告)日：2023-11-16

申请号：US17742628

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Forough Mahmoudabadi ,  Shailesh Kumar Madisetti ,  Van H. Le ,  Timothy Jen ,  Cheng Tan ,  Jisoo Kim ,  Miriam R. Reshotko ,  Vishak Venkatraman ,  Eva Vo ,  Yue Zhong ,  Yu-Che Chiu ,  Moshe Dolejsi ,  Lorenzo Ferrari ,  Akash Kannegulla ,  Deepyanti Taneja ,  Mark Armstrong ,  Kamal H. Baloch ,  Afrin Sultana ,  Albert B. Chen ,  Vamsi Evani ,  Yang Yang ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L27/10805 ,  H01L23/5283 ,  H01L29/78696 ,  H01L29/94

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.