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公开(公告)号:US11496419B2
公开(公告)日:2022-11-08
申请号:US17238893
申请日:2021-04-23
Applicant: Intel Corporation
Inventor: Shaopeng He , Cunming Liang , Jiang Yu , Ziye Yang , Ping Yu , Bo Cui , Jingjing Wu , Liang Ma , Hongjun Ni , Zhiguo Wen , Changpeng Liu , Anjali Singhai Jain , Daniel Daly , Yadong Li
IPC: H04L47/56 , H04L49/9057 , H04L47/34 , H04L1/18 , H04L49/552 , H04L49/90
Abstract: Examples described herein relate to a reliable transport protocol for packet transmission using an Address Family of an eXpress Data Path (AF_XDP) queue framework, wherein the AF_XDP queue framework is to provide a queue for received packet receipt acknowledgements (ACKs). In some examples, an AF_XDP socket is to connect a service with a driver for the network device, one or more queues are associated with the AF_XDP socket, and at least one of the one or more queues comprises a waiting queue for received packet receipt ACKs. In some examples, at least one of the one or more queues is to identify one or more packets for which ACKs have been received. In some examples, the network device is to re-transmit a packet identified by a descriptor in the waiting queue based on non-receipt of an ACK associated with the packet from a receiver.
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公开(公告)号:US11435958B2
公开(公告)日:2022-09-06
申请号:US17253578
申请日:2019-01-31
Applicant: Intel Corporation
Inventor: Gang Cao , Ziye Yang , Xiaodong Liu , Changpeng Liu
Abstract: An apparatus is described. The apparatus includes an accelerator to be coupled to a memory region that the accelerator shares with a virtualization environment comprising a guest OS, a guest VM and an SSD device driver. The accelerator is to forward a submission queue doorbell setting made by the SSD device driver in the shared memory to a corresponding submission queue doorbell in an SSD controller.
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公开(公告)号:US12199888B2
公开(公告)日:2025-01-14
申请号:US18425968
申请日:2024-01-29
Applicant: Intel Corporation
Inventor: Shaopeng He , Cunming Liang , Jiang Yu , Ziye Yang , Ping Yu , Bo Cui , Jingjing Wu , Liang Ma , Hongjun Ni , Zhiguo Wen , Changpeng Liu , Anjali Singhai Jain , Daniel Daly , Yadong Li
IPC: H04L49/9057 , H04L1/1829 , H04L47/34 , H04L47/56 , H04L49/552 , H04L49/90
Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.
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公开(公告)号:US11615194B2
公开(公告)日:2023-03-28
申请号:US16975661
申请日:2018-06-29
Applicant: Intel Corporation
Inventor: Changzheng Wei , Ziye Yang , Junyuan Wang , Cunming Liang , Junhua Hou , Weigang Li , Ping Yu , Yi Yang , Baoqian Li , Xin Zeng
IPC: G06F21/60 , G06F16/14 , H04L9/08 , H04L9/40 , H04L67/1097
Abstract: Embodiments include apparatuses, methods, and systems including one or more servers and one or more storage devices, coupled with each other, to provide virtual storage service to store a file and meta data of the file for a client computing device. The file and the meta data of the file may be encrypted by the client computing device before providing to the virtual storage service. The file may be encrypted with a secret key of the client computing device, and the meta data of the file may be encrypted with a shared session key between the client computing device and the virtual storage service. The encrypted file may be stored in the one or more storage devices, and the encrypted meta data of the file may be stored in one or more secured areas of the one or more servers. Other embodiments may also be described and claimed.
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公开(公告)号:US11372684B2
公开(公告)日:2022-06-28
申请号:US17220763
申请日:2021-04-01
Applicant: Intel Corporation
Inventor: Ned M. Smith , Changzheng Wei , Songwu Shen , Ziye Yang , Junyuan Wang , Weigang Li , Wenqian Yu
Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).
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公开(公告)号:US20210081231A1
公开(公告)日:2021-03-18
申请号:US17041723
申请日:2018-06-29
Applicant: INTEL CORPORATION
Inventor: Ziye Yang
Abstract: Various systems and methods for managing quality of storage service in a virtual network are described herein. A system for managing quality of service in a virtual network includes an analytic platform configured to analyze input/output operations by a virtual host on a storage array in a virtual network, the virtual host identified with a virtual network identifier (VNI), and the virtual network identified by a virtual host address (VHA); and a security controller to: receive, from the analytic platform, storage array metrics associated with the VNI and the VHA; determine that the storage array metrics violate a threshold condition; and cause a responsive action to adjust the operating environment of the virtual host to maintain quality of input/output service for hosts sharing the storage array.
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公开(公告)号:US20200326971A1
公开(公告)日:2020-10-15
申请号:US16464625
申请日:2016-12-28
Applicant: Intel Corporation
Inventor: Ziye Yang
IPC: G06F9/455 , G06F9/54 , G06F15/173 , H04L29/06 , H04L12/46
Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a remote direct memory access (RDMA) message from a first virtual machine located on a first network element, determine that the RDMA message is destined for a second virtual machine that is located on the first network element, and use a local direct memory access engine to process the RDMA message, where the local direct memory access engine is located on the first network element. In an example, the electronic device can be further configured to determine that the RDMA message is destined for a third virtual machine on a second network element, wherein the second network element is different than the first network element and use an other device acceleration driver to process the RDMA message instead of the local direct memory access engine.
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18.
公开(公告)号:US20230259412A1
公开(公告)日:2023-08-17
申请号:US18136972
申请日:2023-04-20
Applicant: Intel Corporation
Inventor: Haokun Xing , Miaomiao Liu , Hualong Feng , Ziye Yang , Junyuan Wang
IPC: G06F9/54
Abstract: Various methods, systems, and use cases for providing a wrapper application programming interface (API). The wrapper API can invoke hardware accelerator libraries based on function calls from cloud native applications.
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公开(公告)号:US11687375B2
公开(公告)日:2023-06-27
申请号:US17724764
申请日:2022-04-20
Applicant: Intel Corporation
Inventor: Ned Smith , Changzheng Wei , Songwu Shen , Ziye Yang , Junyuan Wang , Weigang Li , Wenqian Yu
CPC classification number: G06F9/5044 , G06F9/505 , G06F21/76 , G06F21/602 , G06F2209/509 , Y02D10/00
Abstract: Technologies for hybrid field-programmable gate array (FPGA) application-specific integrated circuit (ASIC) code acceleration are described. In one example, the computing device includes a FPGA comprising: algorithm circuitry to: perform one or more algorithm tasks of an algorithm, wherein the algorithm to perform a service request that is offloaded to the FPGA; and determine a primitive task associated with an algorithm task of the one or more algorithm tasks; primitive offload circuitry to encapsulate the primitive task in a buffer of the FPGA, wherein the buffer is accessible by an ASIC of the computing device; and result circuitry to return one or more results of the service request responsive to performance of the primitive task by the ASIC.
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公开(公告)号:US20230195201A1
公开(公告)日:2023-06-22
申请号:US18110603
申请日:2023-02-16
Applicant: Intel Corporation
Inventor: Junyuan Wang , Timothy Waite , Ziye Yang , Hu Chen , Zixuan Li , Anna Czarnowska , Olayinka Olubayo , Gordon McFadden
CPC classification number: G06F1/324 , G06F9/5094
Abstract: An accelerator apparatus can include an interface to receive service requests from at least one processing core. The accelerator apparatus can include coprocessor circuitry coupled to the interface and comprised of multiple slices. The coprocessor circuitry can detect a performance type for the at least one processing core. The coprocessor circuitry can operate the plurality of coprocessor slices in at least one of a plurality of power modes based on the performance type detected for the at least one processing core. Some operations can be alternatively performed by an operating system on any processor coupled to the network.
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