公开(公告)号：US07281092B2

公开(公告)日：2007-10-09

申请号：US11143328

申请日：2005-06-02

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William E. Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0817 ,  G06F12/0822

摘要： A system and method of managing cache hierarchies with adaptive mechanisms. A preferred embodiment of the present invention includes, in response to selecting a data block for eviction from a memory cache (the source cache) out of a collection of memory caches, examining a data structure to determine whether an entry exists that indicates that the data block has been evicted from the source memory cache, or another peer cache, to a slower cache or memory and subsequently retrieved from the slower cache or memory into the source memory cache or other peer cache. Also, a preferred embodiment of the present invention includes, in response to determining the entry exists in the data structure, selecting a peer memory cache out of the collection of memory caches at the same level in the hierarchy to receive the data block from the source memory cache upon eviction.

摘要翻译： 一种使用自适应机制管理缓存层次结构的系统和方法。 本发明的优选实施例包括响应于从存储器高速缓存的集合中的存储器高速缓存（源高速缓存）中选择用于逐出的数据块，检查数据结构以确定是否存在指示数据 块已经从源存储器高速缓存或另一个对等缓存驱逐到较慢的高速缓存或存储器，并随后从较慢的高速缓存或存储器检索到源存储器高速缓存或其他对等高速缓存。 此外，本发明的优选实施例包括响应于确定条目存在于数据结构中，从层级中的相同级别的存储器高速缓存的集合中选择对等存储器高速缓存以从源接收数据块 内存缓存被驱逐。

公开(公告)号：US20050108496A1

公开(公告)日：2005-05-19

申请号：US10713733

申请日：2003-11-13

申请人： Elmootazbellah Elnozahy ,  James Peterson ,  Ramakrishnan Rajamony ,  Hazim Shafi

发明人： Elmootazbellah Elnozahy ,  James Peterson ,  Ramakrishnan Rajamony ,  Hazim Shafi

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1045

摘要： A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems. For systems with cache memory, any cache entry which is affected by the page move can be updated by modifying its address tag according to the new page mapping. This tag modification may be limited to cache entries in a dirty coherency state. The cache can further relocate a cache entry based on a changed congruence class for any modified address tag.

摘要翻译： 将虚拟存储器分配给数据处理系统中的物理存储器的方法为新的页面映射分配一组连续的物理存储器页面，指示存储器控制器根据新的页面映射移动虚拟存储器页面，然后允许访问 虚拟内存页面使用新页面映射，而内存控制器仍将虚拟内存页面复制到物理内存页面集合。 存储器控制器可以使用临时存储旧页面地址和新页面地址的条目的映射表，并且对于每个条目的拷贝完成，释放条目。 在由存储器控制器完成对存储器页面的复制之前，处理器核心中的翻译后备缓冲器（TLB）条目针对新的页地址进行更新。 本发明可以扩展到非均匀存储器阵列（NUMA）系统。 对于具有缓存内存的系统，可以通过根据新页面映射修改其地址标签来更新受页面移动影响的任何缓存条目。 该标签修改可能被限制在脏相关性状态下的高速缓存条目。 高速缓存可以根据修改后的地址标签的改变的一致性类别进一步重新定位缓存条目。

公开(公告)号：US20050086438A1

公开(公告)日：2005-04-21

申请号：US10687261

申请日：2003-10-16

申请人： James Peterson ,  Ramakrishnan Rajamony ,  Hazim Shafi

发明人： James Peterson ,  Ramakrishnan Rajamony ,  Hazim Shafi

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0817

摘要： A multiprocessor system includes a plurality of data processing nodes. Each node has a processor coupled to a system memory, a cache memory, and a cache directory. The cache directory contains cache coherency information for a predetermined range of system memory addresses. An interconnection enables the nodes to exchange messages. A node initiating a function shipping request identifies an intermediate destination directory based on a list of the function's operands and sends a message indicating the function and its corresponding operands to the identified destination directory. The destination cache directory determines a target node based, at least in part, on its cache coherency status information to reduce memory access latency by selecting a target node where all or some of the operands are valid in the local cache memory. The destination directory then ships the function to the target node over the interconnection.

摘要翻译： 多处理器系统包括多个数据处理节点。 每个节点具有耦合到系统存储器，高速缓存存储器和高速缓存目录的处理器。 缓存目录包含用于系统存储器地址的预定范围的高速缓存一致性信息。 互连使得节点能够交换消息。 启动功能运送请求的节点基于功能的操作数列表识别中间目的地目录，并向指定的目的地目录发送一个指示该功能及其对应操作数的消息。 目的地缓存目录至少部分地基于其高速缓存一致性状态信息来确定目标节点，以通过选择其中全部或某些操作数在本地高速缓冲存储器中有效的目标节点来减少存储器访问等待时间。 目的地目录然后通过互连将功能发送到目标节点。

公开(公告)号：US20050066113A1

公开(公告)日：2005-03-24

申请号：US10666814

申请日：2003-09-18

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Robert Tremaine

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Robert Tremaine

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1631 ,  G06F12/0215

摘要： A method and memory controller for adaptive row management within a memory subsystem provides metrics for evaluating row access behavior and dynamically adjusting the row management policy of the memory subsystem in conformity with measured metrics to reduce the average latency of the memory subsystem. Counters provided within the memory controller track the number of consecutive row accesses and optionally the number of total accesses over a measurement interval. The number of counted consecutive row accesses can be used to control the closing of rows for subsequent accesses, reducing memory latency. The count may be validated using a second counter or storage for improved accuracy and alternatively the row close count may be set via program or logic control in conformity with a count of consecutive row hits in ratio with a total access count. The control of row closure may be performed by a mode selection between always closing a row (non-page mode) or always holding a row open (page mode) or by intelligently closing rows after a count interval (row hold count) determined from the consecutive row access measurements. The logic and counters may be incorporated within the memory controller or within the memory devices and the controller/memory devices may provide I/O ports or memory locations for reading the count values and/or setting a row management mode or row hold count.

摘要翻译： 用于存储器子系统内的自适应行管理的方法和存储器控制器提供用于评估行访问行为的度量，并且根据所测量的度量来动态调整存储器子系统的行管理策略，以减少存储器子系统的平均等待时间。 存储器控制器内提供的计数器跟踪连续行访问的次数，以及可选的测量间隔内总访问次数。 可以使用计数的连续行访问次数来控制后续访问的行关闭，从而减少内存延迟。 可以使用第二计数器或存储器来对计数进行验证，以提高精确度，或者可以通过程序或逻辑控制来设置行关闭计数，这与根据总接入计数的比率的连续行命中的计数一致。 行闭合的控制可以通过总是关闭行（非页面模式）或始终保持行打开（页面模式）之间的模式选择来执行，或者通过在从所述页面模式确定的计数间隔（行保持计数）之后智能地关闭行来执行 连续行访问测量。 逻辑和计数器可以并入存储器控制器内或存储器件内，并且控制器/存储器设备可以提供用于读取计数值的I / O端口或存储器位置和/或设置行管理模式或行保持计数。

公开(公告)号：US08949837B2

公开(公告)日：2015-02-03

申请号：US13434423

申请日：2012-03-29

申请人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

发明人： Patrick Joseph Bohrer ,  Orran Yaakov Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Brett Tremaine

IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F9/38 ,  G06F12/08 ,  G06F9/48

CPC分类号： G06F9/383 ,  G06F9/3851 ,  G06F9/4881 ,  G06F12/0862

摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

摘要翻译： 数据处理系统包括具有访问多级缓存存储器的微处理器。 微处理器执行从源代码对象编译的主线程。 该系统包括用于执行也源自源代码对象的辅助线程的处理器。 辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。 配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。 辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

公开(公告)号：US20070083717A1

公开(公告)日：2007-04-12

申请号：US11245313

申请日：2005-10-06

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Derek Williams ,  Kenneth Wright

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Derek Williams ,  Kenneth Wright

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0822

摘要： A method and data processing system for sequentially coupling successive, homogenous processor requests for a cache line in a chain before the data is received in the cache of a first processor within the chain. Chained intermediate coherency states are assigned to track the chain of processor requests and subsequent access permission provided, prior to receipt of the data at the first processor starting the chain. The chained intermediate coherency state assigned identifies the processor operation and a directional identifier identifies the processor to which the cache line is to be forwarded. When the data is received at the cache of the first processor within the chain, the first processor completes its operation on (or with) the data and then forwards the data to the next processor in the chain. The chain is immediately stopped when a non-homogenous operation is snooped by the last-in-chain processor.

摘要翻译： 一种方法和数据处理系统，用于在数据在链中的第一处理器的高速缓存中接收之前，将链接中的高速缓存行的连续的均匀处理器请求顺序耦合。 分配链接的中间一致性状态，以便在启动链路的第一个处理器接收到数据之前跟踪处理器请求链和后续访问权限。 所分配的链接中间一致性状态标识处理器操作，并且方向标识符标识要向其转发高速缓存行的处理器。 当在链中的第一处理器的高速缓存处接收数据时，第一处理器完成其数据处理（或与数据）的操作，然后将数据转发到链中的下一个处理器。 当最后一个链接处理器窥探非均匀操作时，链条立即停止。

公开(公告)号：US20060155963A1

公开(公告)日：2006-07-13

申请号：US11034546

申请日：2005-01-13

申请人： Patrick Bohrer ,  Orran Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Tremaine

发明人： Patrick Bohrer ,  Orran Krieger ,  Ramakrishnan Rajamony ,  Michael Rosenfield ,  Hazim Shafi ,  Balaram Sinharoy ,  Robert Tremaine

IPC分类号： G06F9/30

CPC分类号： G06F9/383 ,  G06F9/3851 ,  G06F9/4881 ,  G06F12/0862

摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

公开(公告)号：US20060155934A1

公开(公告)日：2006-07-13

申请号：US11032875

申请日：2005-01-11

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William Speight ,  Lixin Zhang

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  William Speight ,  Lixin Zhang

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0804 ,  G06F12/0817

摘要： A system and method for cache management in a data processing system. The data processing system includes a processor and a memory hierarchy. The memory hierarchy includes at least an upper memory cache, at least a lower memory cache, and a write-back data structure. In response to replacing data from the upper memory cache, the upper memory cache examines the write-back data structure to determine whether or not the data is present in the lower memory cache. If the data is present in the lower memory cache, the data is replaced in the upper memory cache without casting out the data to the lower memory cache.

摘要翻译： 一种用于数据处理系统中缓存管理的系统和方法。 数据处理系统包括处理器和存储器层级。 存储器层级至少包括上部存储器高速缓存，至少下部存储器高速缓存和回写数据结构。 响应于从上部存储器高速缓存替换数据，上部存储器高速缓存检查回写数据结构以确定数据是否存在于下部存储器高速缓存中。 如果数据存在于较低存储器高速缓存中，则数据将在上部存储器高速缓存中替换，而不会将数据丢弃到较低的内存高速缓存。

公开(公告)号：US20060064518A1

公开(公告)日：2006-03-23

申请号：US10948407

申请日：2004-09-23

申请人： Patrick Bohrer ,  Ahmed Gheith ,  Peter Hochschild ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  Balaram Sinharoy

发明人： Patrick Bohrer ,  Ahmed Gheith ,  Peter Hochschild ,  Ramakrishnan Rajamony ,  Hazim Shafi ,  Balaram Sinharoy

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A method and apparatus for managing cache injection in a multiprocessor system reduces processing time associated with direct memory access transfers in a symmetrical multiprocessor (SMP) or a non-uniform memory access (NUMA) multiprocessor environment. The method and apparatus either detect the target processor for DMA completion or direct processing of DMA completion to a particular processor, thereby enabling cache injection to a cache that is coupled with processor that executes the DMA completion routine processing the data injected into the cache. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer. Alternatively or in conjunction with target processor identification, an interrupt handler may queue a deferred procedure call to the target processor to process the transferred data. In NUMA multiprocessor systems, the completing processor/target memory is chosen for accessibility of the target memory to the processor and associated cache.

摘要翻译： 用于管理多处理器系统中的高速缓存注入的方法和装置减少与对称多处理器（SMP）或非均匀存储器访问（NUMA）多处理器环境中的直接存储器访问传输相关联的处理时间。 该方法和装置可以检测目标处理器用于DMA完成或直接处理DMA完成到特定处理器，从而使高速缓存注入与执行DMA完成例程的处理器处理注入高速缓存的数据的处理器相连的高速缓存。 可以通过确定处理器处理在DMA传输完成时发生的中断来识别目标处理器。 或者或与目标处理器识别结合，中断处理程序可以将延迟过程调用排队到目标处理器以处理传送的数据。 在NUMA多处理器系统中，选择完成的处理器/目标存储器，以便可访问目标存储器到处理器和相关联的高速缓存。

公开(公告)号：US06711650B1

公开(公告)日：2004-03-23

申请号：US10289817

申请日：2002-11-07

申请人： Patrick Joseph Bohrer ,  Ramakrishnan Rajamony ,  Hazim Shafi

发明人： Patrick Joseph Bohrer ,  Ramakrishnan Rajamony ,  Hazim Shafi

IPC分类号： G06F1202

CPC分类号： G06F12/0835

摘要： A method for accelerating input/output operations within a data processing system is disclosed. Initially, a determination is initially made in a cache controller as to whether or not a bus operation is a data transfer from a first memory to a second memory without intervening communications through a processor, such as a direct memory access (DMA) transfer. If the bus operation is such data transfer, a determination is made in a cache memory as to whether or not the cache memory includes a copy of data from the data transfer. If the cache memory does not include a copy of data from the data transfer, a cache line is allocated within the cache memory to store a copy of data from the data transfer.

摘要翻译： 公开了一种用于加速数据处理系统内的输入/输出操作的方法。 最初，在高速缓存控制器中首先确定总线操作是否是从第一存储器到第二存储器的数据传输，而不需要通过诸如直接存储器访问（DMA）传送的处理器进行通信。 如果总线操作是这种数据传输，则在高速缓冲存储器中确定高速缓冲存储器是否包括来自数据传输的数据的副本。 如果高速缓冲存储器不包括来自数据传输的数据的副本，则在高速缓冲存储器内分配高速缓存线以存储来自数据传输的数据副本。