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    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure
    11.
    发明授权
    Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
    具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺

    公开(公告)号：US06348374B1

    公开(公告)日：2002-02-19

    申请号：US09597887

    申请日：2000-06-19

    申请人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    发明人： Satish D. Athavale ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

    IPC分类号： H01L218242

    CPC分类号： H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10885

    摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.

    摘要翻译： 一种形成垂直晶体管的方法。 在半导体衬底上形成衬垫层。 通过焊盘层和半导体衬底形成槽。 埋在槽中的位线形成。 位线被电介质材料包围。 形成延伸穿过介电材料的带，以将位线连接到半导体衬底。 槽被填充在位线上方的导体。 导体沿其纵向轴线切割，使得导体保持在槽的一侧。 在半导体衬底之上形成基本上与位线正交的字线槽。 导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。 字线形成在连接到单独的栅极导体的字线槽中。

    Vertical DRAM punchthrough stop self-aligned to storage trench
    14.
    发明授权
    Vertical DRAM punchthrough stop self-aligned to storage trench 有权
    垂直DRAM穿透停止自对准到存储沟槽

    公开(公告)号：US06777737B2

    公开(公告)日：2004-08-17

    申请号：US10016605

    申请日：2001-10-30

    申请人： Jack A. Mandelman ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni

    发明人： Jack A. Mandelman ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10885 ,  H01L29/66181 ,  H01L29/945

    摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.

    摘要翻译： 具有小于约90nm的特征尺寸的显示器很少或没有动态电荷损失并且很少或没有陷阱辅助结漏电的半导体存储器结构被提供。 具体地，半导体结构包括存在于含Si衬底中的至少一个背靠背对的沟槽存储存储单元。 每个存储单元包括覆盖沟槽电容器的垂直晶体管。 在沟槽存储单元的每个垂直侧壁上都存在带外扩散，以将每个存储单元的垂直晶体管和沟槽电容器互连到含Si衬底。 穿通阻止掺杂袋位于每个背对背对的沟槽存储存储单元之间，并且其位于相邻存储沟槽的带外扩展之间并且与相邻存储沟槽自对准。

    OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI
    15.
    发明申请
    OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI 有权
    在SOI上用于eDRAM的盒式垂直晶体管

    公开(公告)号：US20050247966A1

    公开(公告)日：2005-11-10

    申请号：US10709450

    申请日：2004-05-06

    申请人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

    发明人： James Adkisson ,  Gary Bronner ,  Dureseti Chidambarrao ,  Ramachandra Divakaruni ,  Carl Radens

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L31/119

    CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L27/10867

    摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

    摘要翻译： 本发明提供了一种形成在绝缘体上硅衬底上的垂直存储器件，其中接触绝缘体上硅衬底的上表面的位线通过上带扩散区域电连接到垂直存储器件 掩埋氧化层。 上带扩散区域通过横向蚀刻掩埋氧化物区域的一部分而形成，其中沉积掺杂多晶硅。 上带区域扩散区域还为垂直存储器件的垂直晶体管提供源极。 垂直存储器件还可以与具有形成在绝缘体上硅衬底上的逻辑器件的支撑区域集成。

    Vertical Fin-FET MOS devices
    19.
    发明授权
    Vertical Fin-FET MOS devices 有权
    垂直Fin-FET MOS器件

    公开(公告)号：US07683428B2

    公开(公告)日：2010-03-23

    申请号：US10597288

    申请日：2004-01-22

    申请人： Dureseti Chidambarrao ,  Jochen Beintner ,  Ramachandra Divakaruni

    发明人： Dureseti Chidambarrao ,  Jochen Beintner ,  Ramachandra Divakaruni

    IPC分类号： H01L27/108

    CPC分类号： H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

    摘要： A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

    摘要翻译： 描述了一种新型的具有低接触电阻的高密度垂直Fin-FET器件。 这些垂直Fin-FET器件具有用作晶体管体的垂直硅“鳍”（12A）。 掺杂的源极和漏极区域（26A，28A）分别形成在鳍片（12A）的底部和顶部。 盖板（24A，24B）沿翅片的侧壁形成。 当适当的偏压被施加到栅极（24A，24B）时，电流垂直地流过源极和漏极区域（26A，28A）之间的鳍片（12A）。 描述了同时形成pFET，nFET，多鳍，单鳍，多栅极和双栅极垂直鳍FET的集成工艺。