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公开(公告)号：US20150332645A1
公开(公告)日：2015-11-19
申请号：US14805134
申请日：2015-07-21
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Hideo SATO , Hiroaki KOMATSU
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0248 , G09G2310/0251 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0297 , G09G2310/08
Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
Abstract translation: 栅极信号线驱动电路包括多个基本电路，每个基本电路向门信号线输出在高信号周期期间为高电平的栅极信号，并在低信号周期期间输出低电平。 每个基本电路包括：玛瑙线高压施加电路，根据高信号周期接通，将高电压施加到栅极信号线; 栅极线路低电压施加电路，其根据低信号周期接通，以将低电压施加到栅极信号线; 以及第二栅极线低电压施加电路，其在关闭栅极线高压应用电路和接通栅极线路的低电压应用之间的至少一部分周期中接通以将低电压施加到栅极信号线 电路。
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Patent Agency Ranking
公开(公告)号：US20150170593A1
公开(公告)日：2015-06-18
申请号：US14546181
申请日：2014-11-18
Inventor： Toshio MIYAZAWA , Iwao TAKEMOTO , Atsushi HASEGAWA , Masahiro MAKI , Kazutaka GOTO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
Abstract translation: 具有移位寄存器的显示驱动电路形成在显示面板上。 移位寄存器包括具有第一和第二晶体管的第一级和具有第三和第四晶体管的第二级。 第一晶体管的控制电极的电压由第一脉冲线的电压从低升高。 在导通状态下，第二晶体管连接第一晶体管的控制电极和恒压线。 第三晶体管的控制电极的电压由第二脉冲线的电压由低变高。 在导通状态下，第四晶体管连接第三晶体管的控制电极和恒压线。 第四晶体管由来自第一级的信号导通。
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公开(公告)号：US20200159357A1
公开(公告)日：2020-05-21
申请号：US16773263
申请日：2020-01-27
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Takayuki SUZUKI
IPC: G06F3/041 , G02F1/1362 , G02F1/1343 , G06F3/044 , G02F1/1345 , G02F1/1333
Abstract: The presence or absence of touch is detected according to a difference of a capacitance caused by the presence or absence of a material that blocks the electric field formed between the detection electrode and the common electrode. The common electrode includes a plurality of divided electrode portions that is extended in a lateral direction and aligned with each other in a longitudinal direction. Each of the plurality of common lines is electrically connected to at least one of the divided electrode portions. The plurality of common lines is arranged in an area next to the common electrode in the lateral direction of the common electrode, arranged next to each other in a width direction orthogonal to a length thereof, is different in width from each other, and the width of the common lines is wider as the length is longer.
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公开(公告)号：US20190156780A1
公开(公告)日：2019-05-23
申请号：US16253647
申请日：2019-01-22
Inventor： Toshio MIYAZAWA , Iwao TAKEMOTO , Atsushi HASEGAWA , Masahiro MAKI , Kazutaka GOTO
IPC: G09G3/36 , G11C19/18 , H01L27/12 , H01L29/423 , G11C19/28
CPC classification number: G09G3/3677 , G09G3/36 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G3/3696 , G09G5/39 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/184 , G11C19/28 , H01L27/12 , H01L27/124 , H01L29/42384
Abstract: A display driving circuit having a shift register is formed on the display panel. The shift register includes a first stage having first and second transistors and a second stage having a third and fourth transistor. A voltage of a control electrode of the first transistor is boosted by a voltage of a first pulse line changing from low to high. In an On state, the second transistor connects the control electrode of the first transistor and a constant voltage line. A voltage of a control electrode of the third transistor is boosted by a voltage of a second pulse line changing from low to high. In an On state, the fourth transistor connects the control electrode of the third transistor and a constant voltage line. The fourth transistor is switched on by a signal from the first stage.
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公开(公告)号：US20160343327A1
公开(公告)日：2016-11-24
申请号：US15227015
申请日：2016-08-03
Applicant: Japan Display Inc.
Inventor： Takayuki SUZUKI , Hiroyuki ABE , Masahiro MAKI , Mitsuru GOTO
IPC: G09G3/36 , G02F1/1333 , G02F1/1335 , G02F1/133 , G06F3/044 , G06F3/041
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
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公开(公告)号：US20150154928A1
公开(公告)日：2015-06-04
申请号：US14615410
申请日：2015-02-05
Applicant: Japan Display Inc.
Inventor： Hiroyuki ABE , Masahiro MAKI , Takayuki SUZUKI
CPC classification number: G09G3/3677 , G09G1/005 , G09G2310/0283 , G09G2310/0286 , G11C19/28
Abstract: A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.
Abstract translation: 显示装置包括：第一级输出电路，其适于对作为彼此并联布置的多个输出信号线中的最终输出信号线的第一级输出信号线进行输出;以及第一级输出电路 包括起始信号线，向该多个输出信号线顺序施加用于施加导通电位的开始信号，施加第一时钟信号的第一时钟信号线，第二时钟信号线，第二时钟信号线 信号被施加，具有连接第一级输出信号线的源极和与第一时钟信号线连接的漏极的第一晶体管和具有连接起始信号线的栅极的第二晶体管 。
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