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公开(公告)号：US20070069269A1
公开(公告)日：2007-03-29
申请号：US11549248
申请日：2006-10-13
IPC分类号： H01L27/108 , H01L29/94 , H01L29/76 , H01L31/119
CPC分类号： H01L28/40 , H01L27/0629 , H01L27/0805
摘要： The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
摘要翻译： 本发明涉及一种堆叠式电容器（10），包括硅基板（16），布置在基板（16）上方的多晶硅中心板（32），下栅极氧化物电介质（26） 板（16）和中心板（32），由中心板（32）上方布置的金属导体制成的盖板（36）和布置在中心板（32）和 盖板（36）。 盖板（36）和基板（16）彼此电连接并一起形成第一电容器电极。 中心板（32）形成第二电容器电极。 本发明还涉及具有这种堆叠电容器的集成电路，以及作为CMOS工艺的一部分的用于制造堆叠电容器的方法。
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公开(公告)号：US07130182B2
公开(公告)日：2006-10-31
申请号：US10830629
申请日：2004-04-22
IPC分类号： H01G4/00
CPC分类号： H01L28/40 , H01L27/0629 , H01L27/0805
摘要： The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.
摘要翻译： 本发明涉及一种堆叠式电容器（10），包括硅基板（16），布置在基板（16）上方的多晶硅中心板（32），下栅极氧化物电介质（26） 板（16）和中心板（32），由中心板（32）上方布置的金属导体制成的盖板（36）和布置在中心板（32）和 盖板（36）。 盖板（36）和基板（16）彼此电连接并一起形成第一电容器电极。 中心板（32）形成第二电容器电极。 本发明还涉及具有这种堆叠电容器的集成电路，以及作为CMOS工艺的一部分的用于制造堆叠电容器的方法。
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公开(公告)号：US20060073672A1
公开(公告)日：2006-04-06
申请号：US11233960
申请日：2005-09-23
IPC分类号： H01L21/76
CPC分类号： H01L27/0623 , H01L21/76229 , H01L21/8249 , H01L27/0207
摘要： An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.
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公开(公告)号：US20050054170A1
公开(公告)日：2005-03-10
申请号：US10928655
申请日：2004-08-26
IPC分类号： H01L21/331 , H01L21/8228 , H01L29/737 , H01L21/44 , H01L21/8222
CPC分类号： H01L29/66242 , H01L21/82285 , H01L29/7378
摘要： Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
摘要翻译： 制造互补SiGe双极晶体管的方法。 在制造互补SiGe双极晶体管的方法中，分别形成用于NPN和PNP发射极（44,64）的界面氧化物层（38,58），发射极多晶硅（40,60）被分开构图，允许这些层被优化 对于各自的导电类型。
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15.发明授权Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection 有权具有栅极自保护的集成电路的制造方法和具有栅极自保护的集成电路公开(公告)号：US07772057B2
公开(公告)日：2010-08-10
申请号：US11470760
申请日：2006-09-07
IPC分类号： H01L21/337
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0251 , H01L27/0705
摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。
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16.发明申请Silicide block isolated junction field effect transistor source, drain and gate 有权硅化物阻隔隔离结场效应晶体管源极，漏极和栅极公开(公告)号：US20080026515A1
公开(公告)日：2008-01-31
申请号：US11493229
申请日：2006-07-26
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0642 , H01L29/66901
摘要： An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.
摘要翻译： 结型场效应晶体管（JFET）用形成栅极，源极和漏极区域的图案化硅化物块（SBLK）材料制成。 以这种方式利用硅化物块有助于通过抑制表面状态的影响来减少与JFET相关的低频（闪烁）噪声。
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公开(公告)号：US07615425B2
公开(公告)日：2009-11-10
申请号：US11504412
申请日：2006-08-15
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0607 , H01L29/66901
摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
摘要翻译： 本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作 。 开路漏极允许电压增加几倍，而不增加晶体管的尺寸。 开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。
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公开(公告)号：US20080042199A1
公开(公告)日：2008-02-21
申请号：US11504412
申请日：2006-08-15
IPC分类号： H01L27/12
CPC分类号： H01L29/808 , H01L29/0607 , H01L29/66901
摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
摘要翻译： 本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作 。 开路漏极允许电压增加几倍，而不增加晶体管的尺寸。 开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。
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19.发明授权Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection 有权具有栅极自保护的集成电路的制造方法和具有栅极自保护的集成电路公开(公告)号：US08294218B2
公开(公告)日：2012-10-23
申请号：US12796386
申请日：2010-06-08
IPC分类号： H01L27/06
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0251 , H01L27/0705
摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.
摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。
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公开(公告)号：US20100136764A1
公开(公告)日：2010-06-03
申请号：US12624442
申请日：2009-11-24
IPC分类号： H01L21/02
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an integrated circuit comprises depositing a electrically resistive layer of a material for serving as a thin film resistor (TFR), depositing an electrically insulating layer on the resistor layer, removing the electrically insulating layer from outside an electrically active area of the resistor layer corresponding to a target TFR area, and depositing an electrically conductive layer of an electrically conductive material such that the conductive layer overlaps the target TFR area and the conductive layer electrically contacts the resistor layer outside the target TFR area.
摘要翻译： 一种制造集成电路的方法包括沉积用作薄膜电阻器（TFR）的材料的电阻层，在电阻层上沉积电绝缘层，从电离层的电活性区域外部去除电绝缘层 对应于目标TFR区域的电阻层，以及沉积导电材料的导电层，使得导电层与靶TFR区域重叠，导电层与目标TFR区域外的电阻层电接触。
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