公开(公告)号：US07091535B2

公开(公告)日：2006-08-15

申请号：US10793972

申请日：2004-03-05

Applicant: Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

Inventor： Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L29/80

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456

Abstract: A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.

Abstract translation: 实现了具有改善的击穿电压的高电压PMOS器件。 不对称的高压集成电路结构包括衬底上的栅极电极和位于栅极电极的任一侧和邻近的衬底内的源极和漏极区域，其中源极区域被n阱包围。 对称的高压集成电路结构包括衬底上的栅极电极，位于栅极电极的任一侧和邻近衬底内的源极和漏极区域以及位于栅极电极下方的衬底中的n-阱。 两个结构中的n阱将击穿点从硅表面移动到源极或漏极区域的底部。

公开(公告)号：US06747336B2

公开(公告)日：2004-06-08

申请号：US09804389

申请日：2001-03-13

Applicant: Jun-Lin Tsai ,  Ruey-Hsing Liu ,  Chiou-Shian Peng ,  Kuo-Chio Liu

Inventor： Jun-Lin Tsai ,  Ruey-Hsing Liu ,  Chiou-Shian Peng ,  Kuo-Chio Liu

IPC: H01L27082

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/732

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract translation: 描述了一种双极性晶体管，其I-V曲线使得其工作在两个区域中，一个具有低增益和低功耗，另一个具有较高的增益和更好的电流驱动能力。 所述晶体管具有由两个子区域构成的基极区域，最靠近发射极的区域的电阻率大约低于第二区域（与集电极接口）的数量级。 本发明的关键特征是最靠近集电极的区域是非常均匀的掺杂的，即没有梯度或内置的场存在。 为了制造这样的区域，使用外延生长以及硼掺杂，而不是诸如离子注入和/或扩散的更常规的技术。

公开(公告)号：US06245609B1

公开(公告)日：2001-06-12

申请号：US09405060

申请日：1999-09-27

Applicant: Jun-Lin Tsai ,  Ruey-Hsin Liu ,  Jei-Feng Hwang ,  Kuo-Chio Liu

Inventor： Jun-Lin Tsai ,  Ruey-Hsin Liu ,  Jei-Feng Hwang ,  Kuo-Chio Liu

IPC: H01L2100

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/7322

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

公开(公告)号：US6162695A

公开(公告)日：2000-12-19

申请号：US376428

申请日：1999-08-18

Applicant: Jei-Feng Hwang ,  Jun-Lin Tsai ,  Ruey-Hsin Liou ,  Kuo-Chio Liu

Inventor： Jei-Feng Hwang ,  Jun-Lin Tsai ,  Ruey-Hsin Liou ,  Kuo-Chio Liu

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8222

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0619 ,  H01L29/0821

Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, placed in an N well region, and located between a base and collector region. The use of the field ring results in an increase in collector-emitter breakdown voltage, as a result of the reduction in local dopant concentration in the N well region. This phenomena, the reduction the local dopant concentration in the N well region, in the vicinity of the field ring region, allows a higher N well dopant concentration to be used, resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated without the field ring regions, and thus with a lower N well dopant concentration.

Abstract translation: 已经开发了用于制造具有同时形成的CMOS器件的共享多个工艺步骤的掩埋层夹持集电极双极（BPCB）器件的方法。 BPCB器件制造序列特征在于使用场环区域，放置在N阱区域中，并且位于基极和集电极区域之间。 作为N阱区域中局部掺杂剂浓度降低的结果，使用场环导致集电极 - 发射极击穿电压的增加。 在场环区域附近，N阱区域中的局部掺杂剂浓度的降低允许使用更高的N阱掺杂剂浓度，导致BPCB器件的频率响应（Ft）增加， 当与没有场环区域制造的对应物相比，并且因此具有较低的N阱掺杂剂浓度时。