Abstract:
A power amplifier (PA) envelope power supply, which provides an envelope power supply signal to radio frequency (RF) PA circuitry, and a process to prevent undershoot of the PA envelope power supply is disclosed. The process includes determining if an envelope control signal to the PA envelope power supply has a step change from a high magnitude to a low magnitude that exceeds a step change limit. Such a step change may cause undershoot of the PA envelope power supply. As such, if the step change exceeds the step change limit, the envelope control signal is modified to use an intermediate magnitude for period of time. Otherwise, if the step change does not exceed the step change limit, the envelope control signal is not modified.
Abstract:
Embodiments of the present disclosure relate to an overlay class F choke of a radio frequency (RF) power amplifier (PA) stage and an RF PA amplifying transistor of the RF PA stage. The overlay class F choke includes a pair of mutually coupled class F inductive elements, which are coupled in series between a PA envelope power supply and a collector of the RF PA amplifying transistor. In one embodiment of the RF PA stage, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. The collector of the RF PA amplifying transistor provides the RF stage output signal. The PA envelope power supply provides an envelope power supply signal to the overlay class F choke. The envelope power supply signal provides power for amplification.
Abstract:
A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.
Abstract:
Radio frequency (RF) power amplifier (PA) circuitry, which transmits RF signals is disclosed. The RF PA circuitry includes a final stage, a final stage current digital-to-analog converter (IDAC), and a final stage temperature compensation circuit. A final stage current reference circuit may provide an uncompensated final stage reference current to the final stage temperature compensation circuit, which receives and temperature compensates the uncompensated final stage reference current to provide a final stage reference current. The final stage IDAC uses the final stage reference current in a digital-to-analog conversion to provide a final stage bias signal to bias the final stage. The temperature compensation provided by the final stage temperature compensation circuit is selectable.
Abstract:
A charge pump of a power amplifier (PA) bias power supply and a process to prevent undershoot disruption of a bias power supply signal of the PA bias power supply are disclosed. The charge pump operates in one of multiple bias supply pump operating modes, which include at least a bias supply pump-up operating mode and a bias supply bypass operating mode. The process prevents selection of the bias supply pump-up operating mode from the bias supply bypass operating mode before charge pump circuitry in the charge pump is capable of providing adequate voltage to prevent undershoot disruption of the bias power supply signal.
Abstract:
At least a first shunt switching element and switching control circuitry of a first switching power supply are disclosed. At least the first shunt switching element is coupled between a ground and an output inductance node of the first switching power supply. The first switching power supply provides a buck output signal from the output inductance node. The switching control circuitry selects one of an ON state and an OFF state of the first shunt switching element. When the buck output signal is above a first threshold, the switching control circuitry is inhibited from selecting the ON state. The first switching power supply provides a first switching power supply output signal based on the buck output signal. By using feedback based on the buck output signal, the switching control circuitry may refine the timing of switching between series switching elements and shunt switching elements to increase efficiency.
Abstract:
Embodiments of the present disclosure relate to multi-mode multi-band radio frequency (RF) power amplifier (PA) circuitry, which includes a multi-mode multi-band quadrature RF PA coupled to multi-mode multi-band switching circuitry via a single output. The switching circuitry provides at least one non-linear mode output and multiple linear mode outputs. The non-linear mode output may be associated with at least one non-linear mode RF communications band and each linear mode output may be associated with a corresponding linear mode RF communications band. The outputs from the switching circuitry may be coupled to an antenna port via front-end aggregation circuitry. The quadrature nature of the quadrature PA path may provide tolerance for changes in antenna loading conditions.
Abstract:
An in-phase radio frequency (RF) power amplifier (PA) stage and a quadrature-phase RF PA stage are disclosed. The in-phase RF PA stage includes a first group of arrays of amplifying transistor elements and the quadrature-phase RF PA stage includes a second group of arrays of amplifying transistor elements. A group of array bias signals is based on a selected one of a group of DDS operating modes. Each of the group of array bias signals is a current signal. The in-phase RF PA stage biases at least one of the first group of arrays of amplifying transistor elements based on the group of array bias signals. Similarly, the quadrature-phase RF PA stage biases at least one of the second group of arrays of amplifying transistor elements based on the group of array bias signals.
Abstract:
A direct current (DC)-DC converter and radio frequency (RF) power amplifier (PA) circuitry are disclosed. The DC-DC converter provides an envelope power supply signal to the RF PA circuitry based on a first power supply output control signal. As a temperature of the RF PA circuitry changes, the envelope power supply signal may need to be adjusted to meet temperature compensation requirements of the RF PA circuitry. With adequate thermal coupling between the DC-DC converter and the RF PA circuitry, adjustments to the envelope power supply signal may be based on temperature measurements of the DC-DC converter. A desired correction of the first power supply output control signal is determined based on a measured temperature of the DC-DC converter and the temperature compensation requirements of the RF PA circuitry. The first power supply output control signal is adjusted based on the desired correction.
Abstract:
Power amplifier (PA) control circuitry and PA bias circuitry are disclosed. During one slot of a multislot transmit burst from radio frequency (RF) PA circuitry, the PA control circuitry selects one PA bias level of the RF PA circuitry and the RF PA circuitry has one output power level. The RF PA circuitry has a next output power level during an adjacent next slot of the multislot transmit burst. If the one output power level exceeds the next output power level by more than a power drop limit, then the PA control circuitry maintains the one PA bias level during the adjacent next slot. If the one output power level significantly exceeds the next output power level, but by less than the power drop limit, then the PA control circuitry selects a next PA bias level, which is less than the one PA bias level, during the adjacent next slot.