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11.发明授权2T2C signal margin test mode using a defined charge and discharge of BL and /BL 失效2T2C信号余量测试模式使用BL和/ BL定义充放电公开(公告)号：US06826099B2
公开(公告)日：2004-11-30
申请号：US10301529
申请日：2002-11-20
IPC分类号： G11C700
摘要： A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译： 半导体存储器测试模式配置包括用于存储数字数据的第一电容器。 第一电容器通过第一选择晶体管将单元板线连接到第一位线，该第一选择晶体管通过与字线的连接被激活。 用于存储数字数据的第二电容器通过第二选择晶体管将单元板线连接到第二位线，第二选择晶体管也通过与字线的连接而被激活。 感测放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。 恒定电流移动器，例如恒定电流吸收器或源极，通过第三晶体管连接到第一位线，用于当第三晶体管导通时改变第一位线上的电荷量，以减小差分读取信号。
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公开(公告)号：US06731554B1
公开(公告)日：2004-05-04
申请号：US10301546
申请日：2002-11-20
申请人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
发明人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
IPC分类号： G11C2900
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines A resistor is connected to one or both of the bit lines through transistors for adding or reducing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译： 本发明提供了一种测试模式部分，用于促进针对信号余量的最坏情况产品测试序列，以确保在整个组件寿命期间的全部产品功能，同时考虑所有的老化效应。 半导体存储器测试模式配置包括：第一电容器，用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据。 第一个选择晶体管通过与字线的连接来激活。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 通过与字线的连接激活第二选择晶体管。 读出放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。电阻器通过晶体管连接到一个或两个位线，用于增加或减少第一和第二位线上的电荷量 当第三晶体管导通时减小差分读取信号的位线。
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公开(公告)号：US07187602B2
公开(公告)日：2007-03-06
申请号：US10250211
申请日：2003-06-13
申请人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
发明人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
CPC分类号： G06F11/1008 , G11C11/22 , G11C29/72
摘要： Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.
摘要翻译： 通过使用冗余来修复ECC检测到的错误，可以提高内存的可靠性。 在一个实施例中，冗余修复由ECC无法纠正的错误。 冗余可以使用电子保险丝，在包含存储器的IC封装后进行维修。 还可以在封装IC之前执行冗余。
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公开(公告)号：US06885597B2
公开(公告)日：2005-04-26
申请号：US10065011
申请日：2002-09-10
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/1204 , G11C2029/5004
摘要： A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
摘要翻译： 公开了一种用于在存储器访问期间测试差分读取信号的测试电路。 测试电路耦合到一对位线。 在读访问期间，所选存储单元在位线上产生差分读信号。 当测试电路被激活时，差分读取信号的幅度是变化的。 这使得能够容易地测试例如存储器IC中的读取信号余量。
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公开(公告)号：US06800890B1
公开(公告)日：2004-10-05
申请号：US10248234
申请日：2002-12-30
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/10817 , H01L27/10852 , H01L27/11507
摘要： An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.
摘要翻译： 公开了具有串联结构的存储器阵列的IC。 串联组的存储单元包括并联耦合到电容器的晶体管。 电容器包括第一和第二副电容器，一个堆叠在另一个之上。 在堆叠中提供具有两个或更多个子电容器的电容器有利地增加电容器的电容而不增加表面积。
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16.发明申请Reference circuit implemented to reduce the degradation of reference capacitors providing reference voltages for 1T1C FeRAM devices 审中-公开实现参考电路，以减少为1T1C FeRAM器件提供参考电压的参考电容的劣化公开(公告)号：US20050063212A1
公开(公告)日：2005-03-24
申请号：US10665401
申请日：2003-09-18
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： A semiconductor memory comprises a first capacitor for storing digital data connecting a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier connected to the first and reference bit-lines measures a differential read signal on the first and reference bit-lines. A toggle flip flop alternately changes the polarization of charge stored on the reference capacitors.
摘要翻译： 半导体存储器包括用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据的第一电容器。 第一个选择晶体管通过与字线的连接来激活。 至少一个参考电容器为参考位线提供参考电压。 连接到第一和参考位线的读出放大器测量第一和参考位线上的差分读取信号。 触发触发器交替地改变存储在参考电容器上的电荷的极化。
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公开(公告)号：US20050033541A1
公开(公告)日：2005-02-10
申请号：US10636369
申请日：2003-08-06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译： 公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。 在写入周期期间，首先将数据写入存储单元。 在第一读取周期期间从存储器单元读取低电平信号。 比较低信号和低参考信号。 比较结果存储在第一存储寄存器中。 在写入周期期间，第二个数据被写入存储单元。 在第二读取周期期间，从存储器单元读取高电平信号。 在高电平信号和高参考信号之间进行比较。 比较结果存储在第二存储寄存器中。 比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出 高参考信号。
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公开(公告)号：US06807084B1
公开(公告)日：2004-10-19
申请号：US10418734
申请日：2003-04-17
IPC分类号： G11C1122
摘要： A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognizing an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.
摘要翻译： 一个FeRAM存储器芯片包括用于存储数据的非易失性二元电容器存储器单元阵列5。 输入引脚接收要存储的数据，以及指示存储单元数组中应存储数据的位置的地址数据。 FeRAM存储器芯片还具有用于识别外部施加的复位信号的复位单元7。 复位单元7在识别到复位信号时启动复位操作，其中存储在存储单元中的数据的至少一部分被设置为预定值。
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公开(公告)号：US06731529B2
公开(公告)日：2004-05-04
申请号：US10161907
申请日：2002-06-04
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , H01L27/108 , H01L27/10814
摘要： A memory chain with capacitors having different capacitances, depending on the location of the memory cell within the chain, is described. Varying the capacitances of the capacitors advantageously enables an effective capacitance for all memory cells within the chain to be about the same.
摘要翻译： 描述了具有不同电容的电容器的存储器链，这取决于链中存储器单元的位置。 改变电容器的电容有利地使链中所有存储单元的有效电容大致相同。
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