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公开(公告)号：US06731529B2
公开(公告)日：2004-05-04
申请号：US10161907
申请日：2002-06-04
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , H01L27/108 , H01L27/10814
摘要： A memory chain with capacitors having different capacitances, depending on the location of the memory cell within the chain, is described. Varying the capacitances of the capacitors advantageously enables an effective capacitance for all memory cells within the chain to be about the same.
摘要翻译： 描述了具有不同电容的电容器的存储器链，这取决于链中存储器单元的位置。 改变电容器的电容有利地使链中所有存储单元的有效电容大致相同。
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公开(公告)号：US06639824B1
公开(公告)日：2003-10-28
申请号：US10065126
申请日：2002-09-19
申请人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
发明人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.
摘要翻译： 描述了具有分组排列的存储单元的IC。 存储单元例如是铁电存储单元。 该IC包括一个可变电压发生器（VVG），用于根据存储器组内寻址的存储器单元的位置产生具有不同电压电平的输出电压。 通过为读取和/或写入提供不同的电压电平，可以避免由取决于组内的存储器单元的位置的电容引起的信号损失。 这改善了串行存储器架构中的读取和/或写入操作。
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公开(公告)号：US06999887B2
公开(公告)日：2006-02-14
申请号：US10636369
申请日：2003-08-06
IPC分类号： G06F3/06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译： 公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。 在写入周期期间，首先将数据写入存储单元。 在第一读取周期期间从存储器单元读取低电平信号。 比较低信号和低参考信号。 比较结果存储在第一存储寄存器中。 在写入周期期间，第二个数据被写入存储单元。 在第二读取周期期间，从存储器单元读取高电平信号。 在高电平信号和高参考信号之间进行比较。 比较结果存储在第二存储寄存器中。 比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出 高参考信号。
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4.发明授权Reducing effects of noise coupling in integrated circuits with memory arrays 失效降低与存储器阵列集成电路中噪声耦合的影响公开(公告)号：US06920059B2
公开(公告)日：2005-07-19
申请号：US10065921
申请日：2002-11-29
申请人： Michael Jacob , Thomas Roehr , Norbert Rehm , Daisaburo Takashima
发明人： Michael Jacob , Thomas Roehr , Norbert Rehm , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.
摘要翻译： 公开了一种减少存储器阵列中的噪声耦合的方法。 存储器阵列包括通过字线，位线和平行线互连的多个存储器单元。 存储单元被布置成具有耦合到读出放大器的第一和第二位线的列。 在存储器访问期间，至少相邻的位线对不被激活。 选定的位线对或对配有一条平行线脉冲。
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5.发明申请Reference circuit implemented to reduce the degradation of reference capacitors providing reference voltages for 1T1C FeRAM devices 审中-公开实现参考电路，以减少为1T1C FeRAM器件提供参考电压的参考电容的劣化公开(公告)号：US20050063212A1
公开(公告)日：2005-03-24
申请号：US10665401
申请日：2003-09-18
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： A semiconductor memory comprises a first capacitor for storing digital data connecting a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier connected to the first and reference bit-lines measures a differential read signal on the first and reference bit-lines. A toggle flip flop alternately changes the polarization of charge stored on the reference capacitors.
摘要翻译： 半导体存储器包括用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据的第一电容器。 第一个选择晶体管通过与字线的连接来激活。 至少一个参考电容器为参考位线提供参考电压。 连接到第一和参考位线的读出放大器测量第一和参考位线上的差分读取信号。 触发触发器交替地改变存储在参考电容器上的电荷的极化。
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公开(公告)号：US20050033541A1
公开(公告)日：2005-02-10
申请号：US10636369
申请日：2003-08-06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译： 公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。 在写入周期期间，首先将数据写入存储单元。 在第一读取周期期间从存储器单元读取低电平信号。 比较低信号和低参考信号。 比较结果存储在第一存储寄存器中。 在写入周期期间，第二个数据被写入存储单元。 在第二读取周期期间，从存储器单元读取高电平信号。 在高电平信号和高参考信号之间进行比较。 比较结果存储在第二存储寄存器中。 比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出 高参考信号。
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公开(公告)号：US06731554B1
公开(公告)日：2004-05-04
申请号：US10301546
申请日：2002-11-20
申请人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
发明人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
IPC分类号： G11C2900
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines A resistor is connected to one or both of the bit lines through transistors for adding or reducing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译： 本发明提供了一种测试模式部分，用于促进针对信号余量的最坏情况产品测试序列，以确保在整个组件寿命期间的全部产品功能，同时考虑所有的老化效应。 半导体存储器测试模式配置包括：第一电容器，用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据。 第一个选择晶体管通过与字线的连接来激活。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 通过与字线的连接激活第二选择晶体管。 读出放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。电阻器通过晶体管连接到一个或两个位线，用于增加或减少第一和第二位线上的电荷量 当第三晶体管导通时减小差分读取信号的位线。
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8.发明授权公开(公告)号：US06898104B2
公开(公告)日：2005-05-24
申请号：US10291610
申请日：2002-11-12
申请人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
发明人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.
摘要翻译： 半导体器件包括存储单元阵列，与位线互补的位线/ /位线，参考电压产生电路和读出放大器。 位线连接到存储器单元并且被施加从存储单元阵列的每个存储单元读取的电压。 /位线提供参考电压。 参考电压产生电路产生具有温度依赖性的参考电压，用于补偿由温度读取到位线的电压变化。 参考电压产生电路控制参考电压，使得参考电压采取指示“0”数据的信号值分布的轨迹的中点和指示“1”数据的信号值分布。 读出放大器将读取到位线的电压与提供给/位线的参考电压进行比较，并放大它们之间的差值。
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公开(公告)号：US20050146918A1
公开(公告)日：2005-07-07
申请号：US11059569
申请日：2005-02-17
申请人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
发明人： Ryu Ogiwara , Daisaburo Takashima , Michael Jacob
摘要： A semiconductor device comprises a memory cell array, bit line, /bit line complementary to the bit line, reference voltage generating circuit and sense amplifier. The bit line is connected to the memory cells and applied with a voltage read from each memory cell of the memory cell array. The /bit line is supplied with a reference voltage. The reference voltage generating circuit generates the reference voltage that has temperature dependence for compensating a change in the voltage, read to the bit line, due to temperature. The reference voltage generating circuit controls the reference voltage such that the reference voltage assumes a midpoint of trails of a signal value distribution indicative of “0” data and a signal value distribution indicative of “1” data. The sense amplifier compares the voltage, read to the bit line, with the reference voltage supplied to the /bit line, and amplifies the difference therebetween.
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公开(公告)号：US07187602B2
公开(公告)日：2007-03-06
申请号：US10250211
申请日：2003-06-13
申请人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
发明人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
CPC分类号： G06F11/1008 , G11C11/22 , G11C29/72
摘要： Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.
摘要翻译： 通过使用冗余来修复ECC检测到的错误，可以提高内存的可靠性。 在一个实施例中，冗余修复由ECC无法纠正的错误。 冗余可以使用电子保险丝，在包含存储器的IC封装后进行维修。 还可以在封装IC之前执行冗余。
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