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公开(公告)号：US20110161642A1
公开(公告)日：2011-06-30
申请号：US12649805
申请日：2009-12-30
IPC分类号： G06F9/32
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.
摘要翻译： 提供了在运行时提取数据依赖关系的机制。 利用这些机制，执行具有循环的一部分代码。 为该循环生成第一个并行执行组，该组包括小于循环迭代总次数的循环迭代子集。 通过并行执行每个迭代来执行第一个并行执行组。 存储用于迭代的数据存储在处理器的相应存储高速缓存中。 处理器的依赖性检查逻辑为每次迭代确定迭代是否具有数据依赖性。 只有确定了没有数据依赖关系的商店的商店数据被提交到内存。
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12.发明申请Data Parallel Function Call for Determining if Called Routine is Data Parallel 失效数据并行函数调用确定调用例程是否是数据并行的公开(公告)号：US20110161623A1
公开(公告)日：2011-06-30
申请号：US12649751
申请日：2009-12-30
CPC分类号： G06F9/30072 , G06F8/456 , G06F9/30189 , G06F9/3851 , G06F9/3887
摘要： Mechanisms for performing data parallel function calls in code during runtime are provided. These mechanisms may operate to execute, in the processor, a portion of code having a data parallel function call to a target portion of code. The mechanisms may further operate to determine, at runtime by the processor, whether the target portion of code is a data parallel portion of code or a scalar portion of code and determine whether the calling code is data parallel code or scalar code. Moreover, the mechanisms may operate to execute the target portion of code based on the determination of whether the target portion of code is a data parallel portion of code or a scalar portion of code, and the determination of whether the calling code is data parallel code or scalar code.
摘要翻译： 提供了在运行期间执行代码中数据并行函数调用的机制。 这些机制可以操作以在处理器中执行具有对目标代码部分的数据并行函数调用的代码的一部分。 这些机制可以进一步操作以在运行时由处理器确定目标代码部分是代码的数据并行部分还是代码的标量部分，并确定调用代码是数据并行代码还是标量代码。 此外，这些机制可以基于代码的目标部分是代码的数据并行部分还是代码的标量部分的确定来执行代码的目标部分，以及确定调用代码是否是数据并行代码 或标量代码。
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公开(公告)号：US07861022B2
公开(公告)日：2010-12-28
申请号：US12393469
申请日：2009-02-26
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
CPC分类号： G06F11/362 , G06F11/0724 , G06F11/0757
摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译： 提供了用于解决多处理器数据处理系统中的活动锁定状态的机制。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。
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14.发明授权Method, system, and computer program product for displaying images of conference call participants 有权用于显示电话会议参与者图像的方法，系统和计算机程序产品公开(公告)号：US07792263B2
公开(公告)日：2010-09-07
申请号：US11354426
申请日：2006-02-15
申请人： Bruce D. D'Amora , Charles R. Johns
发明人： Bruce D. D'Amora , Charles R. Johns
IPC分类号： H04M7/00
CPC分类号： H04N7/152
摘要： The present invention provides a method, system, and computer program product for displaying images of conference call participants. A method in accordance with an embodiment of the present invention includes receiving a call from a user to join a conference call, obtaining a phone number of the user, matching the phone number to a stored graphical representation, and distributing and displaying the matching graphical representation to a predetermined set of users. A voice identification/recognition process can also be used to match the user to a stored graphical representation.
摘要翻译： 本发明提供了一种用于显示电话会议参与者的图像的方法，系统和计算机程序产品。 根据本发明的实施例的方法包括从用户接收加入电话会议的呼叫，获得用户的电话号码，将电话号码与存储的图形表示相匹配，以及分发和显示匹配的图形表示 到预定的一组用户。 语音识别/识别过程也可以用于将用户与存储的图形表示相匹配。
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15.发明授权Method for communicating instructions and data between a processor and external devices 失效在处理器和外部设备之间传送指令和数据的方法公开(公告)号：US07778271B2
公开(公告)日：2010-08-17
申请号：US11207970
申请日：2005-08-19
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和外部设备之间传送指令和数据的方法。 该方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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16.发明申请Digital Thermal Sensor Test Implementation Without Using Main Core Voltage Supply 失效数字热传感器测试实现，不使用主芯电压公开(公告)号：US20090125267A1
公开(公告)日：2009-05-14
申请号：US11937134
申请日：2007-11-08
IPC分类号： G01K15/00
CPC分类号： G01K15/00 , G01K15/005
摘要： A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.
摘要翻译： 提供了一种用于校准数字热传感器的方法和装置。 具有多个数字热传感器的处理器芯片接收模拟电压。 耦合到处理器芯片的测试电路接收时钟信号，耦合到测试电路的寄存器将每个时钟周期上的值输出到多个数字热传感器中的数字热传感器。 数字热传感器响应于数字热传感器中接收的寄存器的值等于数字热传感器的温度阈值而转换输出状态。 在转换点处的寄存器的值用于校准数字热传感器。 响应于数字热敏传感器接收到的寄存器的值不能等于数字热传感器的温度阈值，增量器会在每个时钟周期内递增寄存器的值。
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17.发明申请公开(公告)号：US20080104711A1
公开(公告)日：2008-05-01
申请号：US11553008
申请日：2006-10-26
申请人： Charles R. Johns , Kanna Shimizu
发明人： Charles R. Johns , Kanna Shimizu
IPC分类号： H04L9/32 , G06F17/30 , H04L9/00 , G06F12/14 , G06F7/04 , G06K9/00 , G06F11/30 , H03M1/68 , H04K1/00 , H04N7/16
CPC分类号： G06F12/145 , G06F21/53
摘要： A system, method, and computer-usable medium for an isolated process to control address translation. According to a preferred embodiment of the present invention, an isolation region that is accessible only to a first processing unit in a data processing system is created. A loader is executed to load a secure process in the isolation region. If the secure process is determined to be allowed to issue real mode direct memory access commands, real mode direct memory access commands are enabled to allow the secure process to issue non-translated direct memory access commands.
摘要翻译： 用于控制地址转换的隔离过程的系统，方法和计算机可用介质。 根据本发明的优选实施例，创建了仅在数据处理系统中的第一处理单元可访问的隔离区域。 执行加载器以在隔离区域中加载安全处理。 如果确定安全过程被允许发出实模式直接存储器访问命令，则启用实模式直接存储器访问命令以允许安全过程发出非转换的直接存储器访问命令。
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18.发明申请公开(公告)号：US20070298886A1
公开(公告)日：2007-12-27
申请号：US11425452
申请日：2006-06-21
IPC分类号： A63F9/24
CPC分类号： G06N3/006 , A63F13/49 , A63F13/55 , A63F13/822 , A63F13/85 , A63F2300/537 , A63F2300/575 , G07F17/32
摘要： A mechanism is provided for configuring offline player behavior within a persistent world game. A player agent for an offline player includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent may generate game events on behalf of the offline player. The player agent may also receive messages from an offline player. The messages may include commands for adding, removing, or editing offline player rules. A message may also include a command to view a list of rules or fire a one-time execution of a rule upon receipt. Therefore, a player may contribute to the persistent virtual world even when offline by sending commands using a messaging client or Web browser.
摘要翻译： 提供了一种用于在持久化世界游戏中配置离线玩家行为的机制。 用于离线播放器的播放器代理包括事件监视器，其监视由游戏服务器维护的持久虚拟世界中发生的事件。 当发生触发离线玩家规则的游戏事件时，玩家代理可以代表离线玩家生成游戏事件。 播放器代理也可以从离线播放器接收消息。 消息可能包括用于添加，删除或编辑离线播放器规则的命令。 消息还可以包括查看规则列表的命令或者在接收到一次规则执行时触发。 因此，即使当通过使用消息传递客户端或Web浏览器发送命令进行脱机时，玩家也可以对持久虚拟世界作出贡献。
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公开(公告)号：US09053069B2
公开(公告)日：2015-06-09
申请号：US13593030
申请日：2012-08-23
IPC分类号： G06F15/173
CPC分类号： G06F15/17337
摘要： A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel.
摘要翻译： 提供了一种用于生成器/消费者缓冲器状态的有效通信的机制。 利用该机制，当设备使用设备的信号通知通道在共享缓冲区域上执行操作时，数据处理系统中的设备通知彼此对共享缓冲区域的头和尾指针的更新。 因此，当向共享缓冲区域产生数据的生成器设备将数据写入到共享缓冲区域时，对头指针的更新被写入消费者设备的信号通知通道。 当消费者设备从共享缓冲区域读取数据时，消费者设备将尾指针更新写入生成器设备的信号通知通道。 此外，信道可以以阻塞模式操作，使得对应的设备保持在低功率状态，直到通过信道接收到更新。
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20.发明授权Structure for performing cacheline polling utilizing a store and reserve instruction 有权使用存储和预留指令进行缓存线轮询的结构公开(公告)号：US09009420B2
公开(公告)日：2015-04-14
申请号：US13426840
申请日：2012-03-22
申请人： Charles R. Johns
发明人： Charles R. Johns
CPC分类号： G06F12/0806 , G06F9/52 , G06F2209/521
摘要： A design structure for performing cacheline polling utilizing a store and reserve instruction are disclosed. In accordance with one embodiment of the present invention, a first process initially requests an action to be performed by a second process. A reservation is set at a cacheable memory location via a store operation. The first process reads the cacheable memory location via a load operation to determine whether or not the requested action has been completed by the second process. The load operation of the first process is stalled until the reservation on the cacheable memory location is lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.
摘要翻译： 公开了一种使用存储和预约指令执行高速缓存行轮询的设计结构。 根据本发明的一个实施例，第一过程最初请求通过第二过程执行动作。 通过存储操作在可高速缓存的存储器位置设置预留。 第一进程通过加载操作读取可高速缓存的存储器位置，以确定所请求的动作是否已由第二进程完成。 第一个进程的加载操作停止，直到可缓存的内存位置的预留丢失。 在请求的动作完成之后，可缓存存储器位置中的预留由第二进程复位。
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